Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *    ATBM8830, ATBM8831
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ATBM8830_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ATBM8830_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct atbm_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	/* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	const struct atbm8830_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_CHIP_ID	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_TUNER_BASEBAND	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_DEMOD_RUN	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_DSP_RESET	0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_RAM_RESET	0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_ADC_RESET	0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_TSPORT_RESET	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_BLKERR_POL	0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_I2C_GATE	0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_TS_SAMPLE_EDGE	0x0301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_TS_PKT_LEN_204	0x0302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_TS_PKT_LEN_AUTO	0x0303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_TS_SERIAL	0x0305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_TS_CLK_FREERUN	0x0306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_TS_VALID_MODE	0x0307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_TS_CLK_MODE	0x030B /* 1 for serial, 0 for parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_TS_ERRBIT_USE	0x030C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_LOCK_STATUS	0x030D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_ADC_CONFIG	0x0602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_CARRIER_OFFSET	0x0827 /* 0x0827-0x0829 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_DETECTED_PN_MODE	0x082D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_READ_LATCH	0x084D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_IF_FREQ	0x0A00 /* 0x0A00-0x0A02 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_OSC_CLK	0x0A03 /* 0x0A03-0x0A05 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_BYPASS_CCI	0x0A06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_ANALOG_LUMA_DETECTED	0x0A25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_ANALOG_AUDIO_DETECTED	0x0A26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_ANALOG_CHROMA_DETECTED	0x0A39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_FRAME_ERR_CNT	0x0B04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_USE_EXT_ADC	0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_SWAP_I_Q	0x0C01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_TPS_MANUAL	0x0D01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_TPS_CONFIG	0x0D02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_BYPASS_DEINTERLEAVER	0x0E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_AGC_TARGET	0x1003 /* 0x1003-0x1005 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_AGC_MIN	0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_AGC_MAX	0x1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_AGC_LOCK	0x1027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_AGC_PWM_VAL	0x1028 /* 0x1028-0x1029 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_AGC_HOLD_LOOP	0x1031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)