Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *    ATBM8830, ATBM8831
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "atbm8830.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "atbm8830_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 			printk(KERN_DEBUG "atbm8830: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u8 buf1[] = { reg >> 8, reg & 0xFF };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u8 buf2[] = { data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	dev_addr = priv->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	msg1.addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	msg2.addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (debug >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		dprintk("%s: reg=0x%04X, data=0x%02X\n", __func__, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	ret = i2c_transfer(priv->i2c, &msg1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	ret = i2c_transfer(priv->i2c, &msg2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return (ret != 1) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 buf1[] = { reg >> 8, reg & 0xFF };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 buf2[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	dev_addr = priv->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	msg1.addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	msg2.addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ret = i2c_transfer(priv->i2c, &msg1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		dprintk("%s: error reg=0x%04x, ret=%i\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret = i2c_transfer(priv->i2c, &msg2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	*p_data = buf2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (debug >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		dprintk("%s: reg=0x%04X, data=0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			__func__, reg, buf2[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* Lock register latch so that multi-register read is atomic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* 0x100000 * freq / 30.4MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	t = (u64)0x100000 * freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	do_div(t, 30400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	val = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	atbm8830_write_reg(priv, REG_OSC_CLK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 fs = priv->config->osc_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8 dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (freq != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		/* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		t = (u64) 2 * 31416 * (freq - fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		t <<= 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		do_div(t, fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		do_div(t, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		val = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		atbm8830_write_reg(priv, REG_IF_FREQ, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		dat &= 0xFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		/* Zero IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		dat &= 0xFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		dat |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (priv->config->zif_swap_iq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int is_locked(struct atbm_state *priv, u8 *locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (locked != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		*locked = (status == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int set_agc_config(struct atbm_state *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u8 min, u8 max, u8 hold_loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* no effect if both min and max are zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (!min && !max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	    return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	atbm8830_write_reg(priv, REG_AGC_MIN, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	atbm8830_write_reg(priv, REG_AGC_MAX, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	atbm8830_write_reg(priv, REG_AGC_HOLD_LOOP, hold_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int set_static_channel_mode(struct atbm_state *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		atbm8830_write_reg(priv, 0x099B + i, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	atbm8830_write_reg(priv, 0x095B, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	atbm8830_write_reg(priv, 0x09CB, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	atbm8830_write_reg(priv, 0x09CC, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	atbm8830_write_reg(priv, 0x09CD, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	atbm8830_write_reg(priv, 0x0E01, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* For single carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	atbm8830_write_reg(priv, 0x0B03, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	atbm8830_write_reg(priv, 0x0935, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	atbm8830_write_reg(priv, 0x0936, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	atbm8830_write_reg(priv, 0x093E, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	atbm8830_write_reg(priv, 0x096E, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* frame_count_max0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	atbm8830_write_reg(priv, 0x0B09, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* frame_count_max1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	atbm8830_write_reg(priv, 0x0B0A, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int set_ts_config(struct atbm_state *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	const struct atbm8830_config *cfg = priv->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/*Set parallel/serial ts mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/*Set ts sampling edge*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		cfg->ts_sampling_edge ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/*Set ts clock freerun*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		cfg->ts_clk_gated ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int atbm8830_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	const struct atbm8830_config *cfg = priv->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/*Set oscillator frequency*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	set_osc_freq(priv, cfg->osc_clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/*Set IF frequency*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	set_if_freq(priv, cfg->if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*Set AGC Config*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	set_agc_config(priv, cfg->agc_min, cfg->agc_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		cfg->agc_hold_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/*Set static channel mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	set_static_channel_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	set_ts_config(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*Turn off DSP reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	atbm8830_write_reg(priv, 0x000A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*SW version test*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	atbm8830_write_reg(priv, 0x020C, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void atbm8830_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct atbm_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int atbm8830_set_fe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	u8 locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* set frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* start auto lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		dprintk("Try %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		is_locked(priv, &locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		if (locked != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			dprintk("ATBM8830 locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int atbm8830_get_fe(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			   struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* TODO: get real readings from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* inversion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	c->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	c->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	c->code_rate_HP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	c->code_rate_LP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	c->modulation = QAM_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* transmission mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	c->transmission_mode = TRANSMISSION_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* guard interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	c->guard_interval = GUARD_INTERVAL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct dvb_frontend_tune_settings *fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	fesettings->min_delay_ms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int atbm8830_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				enum fe_status *fe_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	u8 locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	u8 agc_locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	*fe_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	is_locked(priv, &locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (locked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		*fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dprintk("AGC Lock: %d\n", agc_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u32 frame_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	atbm8830_reglatch_lock(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	frame_err = t & 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	frame_err <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	frame_err |= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	atbm8830_reglatch_lock(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	*ber = frame_err * 100 / 32767;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	dprintk("%s: ber=0x%x\n", __func__, *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	u32 pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	atbm8830_reglatch_lock(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	pwm = t & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pwm <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	pwm |= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	atbm8830_reglatch_lock(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	dprintk("AGC PWM = 0x%02X\n", pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pwm = 0x400 - pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	*signal = pwm * 0x10000 / 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	*snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	*ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct atbm_state *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct dvb_frontend_ops atbm8830_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.delsys = { SYS_DTMB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		.name = "AltoBeam ATBM8830/8831 DMB-TH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.frequency_min_hz = 474 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		.frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		.frequency_stepsize_hz = 10 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			FE_CAN_GUARD_INTERVAL_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.release = atbm8830_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.init = atbm8830_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.sleep = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.write = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.set_frontend = atbm8830_set_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.get_frontend = atbm8830_get_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.get_tune_settings = atbm8830_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.read_status = atbm8830_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.read_ber = atbm8830_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.read_signal_strength = atbm8830_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.read_snr = atbm8830_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	.read_ucblocks = atbm8830_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	struct atbm_state *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (config == NULL || i2c == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	priv->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	/* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			__func__, priv->config->demod_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	dprintk("atbm8830 chip id: 0x%02X\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	memcpy(&priv->frontend.ops, &atbm8830_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	       sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	priv->frontend.demodulator_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	atbm8830_init(&priv->frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	return &priv->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	dprintk("%s() error_out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) EXPORT_SYMBOL(atbm8830_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_LICENSE("GPL");