^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Afatech AF9033 demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef AF9033_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AF9033_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * I2C address: 0x1c, 0x1d, 0x1e, 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct af9033_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * clock Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 12000000, 22000000, 24000000, 34000000, 32000000, 28000000, 26000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 30000000, 36000000, 20480000, 16384000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ADC multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AF9033_ADC_MULTIPLIER_1X 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AF9033_ADC_MULTIPLIER_2X 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 adc_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AF9033_TUNER_TUA9001 0x27 /* Infineon TUA 9001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AF9033_TUNER_FC0011 0x28 /* Fitipower FC0011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AF9033_TUNER_FC0012 0x2e /* Fitipower FC0012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AF9033_TUNER_MXL5007T 0xa0 /* MaxLinear MxL5007T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AF9033_TUNER_TDA18218 0xa1 /* NXP TDA 18218HN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AF9033_TUNER_FC2580 0x32 /* FCI FC2580 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* 50-5f Omega */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AF9033_TUNER_IT9135_38 0x38 /* Omega */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AF9033_TUNER_IT9135_51 0x51 /* Omega LNA config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AF9033_TUNER_IT9135_52 0x52 /* Omega LNA config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 60-6f Omega v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AF9033_TUNER_IT9135_60 0x60 /* Omega v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AF9033_TUNER_IT9135_61 0x61 /* Omega v2 LNA config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AF9033_TUNER_IT9135_62 0x62 /* Omega v2 LNA config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * TS settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AF9033_TS_MODE_USB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AF9033_TS_MODE_PARALLEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AF9033_TS_MODE_SERIAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 ts_mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * input spectrum inversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bool dyn0_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * PID filter ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct af9033_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * frontend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * returned by that driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dvb_frontend **fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * regmap for IT913x integrated tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * returned by that driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct af9033_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*pid_filter_ctrl)(struct dvb_frontend *fe, int onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int (*pid_filter)(struct dvb_frontend *fe, int index, u16 pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif /* AF9033_H */