^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Afatech AF9033 demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "af9033_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct af9033_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct dvb_frontend fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct af9033_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) bool is_af9035;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) bool is_it9135;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bool ts_mode_parallel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) bool ts_mode_serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum fe_status fe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u64 post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u64 post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u64 error_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u64 total_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Write reg val table using reg addr auto increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct reg_val *tab, int tab_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_TAB_LEN 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 buf[1 + MAX_TAB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (tab_len > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) for (i = 0, j = 0; i < tab_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) buf[j] = tab[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) buf, j + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int af9033_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret, i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct reg_val *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct reg_val_mask tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0x80fb24, 0x00, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0x80004c, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0x00f641, dev->cfg.tuner, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0x80f5ca, 0x01, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0x80f715, 0x01, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0x00f41f, 0x04, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0x00f41a, 0x01, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0x80f731, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0x00d91e, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0x00d919, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0x80f732, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0x00d91f, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0x00d91a, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0x80f730, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0x80f778, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x80f73c, 0x01, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0x80f776, 0x00, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 0x00d8fd, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 0x00d830, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0x00d831, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 0x00d832, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0x80f985, dev->ts_mode_serial, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0x80f986, dev->ts_mode_parallel, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0x00d827, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x00d829, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x800045, dev->cfg.adc_multiplier, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Main clk control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) buf[0] = (utmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) buf[1] = (utmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) buf[2] = (utmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) buf[3] = (utmp >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* ADC clk control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (clock_adc_lut[i].clock == dev->cfg.clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (i == ARRAY_SIZE(clock_adc_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev->cfg.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) buf[0] = (utmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) buf[1] = (utmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) buf[2] = (utmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clock_adc_lut[i].adc, utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Config register table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < ARRAY_SIZE(tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tab[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Demod clk output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (dev->cfg.dyn0_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* TS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Demod core settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(&client->dev, "load ofsm settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (dev->cfg.tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case AF9033_TUNER_IT9135_38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case AF9033_TUNER_IT9135_51:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case AF9033_TUNER_IT9135_52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) len = ARRAY_SIZE(ofsm_init_it9135_v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) init = ofsm_init_it9135_v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case AF9033_TUNER_IT9135_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case AF9033_TUNER_IT9135_61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case AF9033_TUNER_IT9135_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) len = ARRAY_SIZE(ofsm_init_it9135_v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) init = ofsm_init_it9135_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) len = ARRAY_SIZE(ofsm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) init = ofsm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = af9033_wr_reg_val_tab(dev, init, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Demod tuner specific settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_dbg(&client->dev, "load tuner specific settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (dev->cfg.tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case AF9033_TUNER_TUA9001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) len = ARRAY_SIZE(tuner_init_tua9001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) init = tuner_init_tua9001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case AF9033_TUNER_FC0011:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) len = ARRAY_SIZE(tuner_init_fc0011);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) init = tuner_init_fc0011;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case AF9033_TUNER_MXL5007T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) len = ARRAY_SIZE(tuner_init_mxl5007t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) init = tuner_init_mxl5007t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case AF9033_TUNER_TDA18218:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) len = ARRAY_SIZE(tuner_init_tda18218);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) init = tuner_init_tda18218;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case AF9033_TUNER_FC2580:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) len = ARRAY_SIZE(tuner_init_fc2580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) init = tuner_init_fc2580;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case AF9033_TUNER_FC0012:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) len = ARRAY_SIZE(tuner_init_fc0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) init = tuner_init_fc0012;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case AF9033_TUNER_IT9135_38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) len = ARRAY_SIZE(tuner_init_it9135_38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) init = tuner_init_it9135_38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case AF9033_TUNER_IT9135_51:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) len = ARRAY_SIZE(tuner_init_it9135_51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) init = tuner_init_it9135_51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case AF9033_TUNER_IT9135_52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) len = ARRAY_SIZE(tuner_init_it9135_52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) init = tuner_init_it9135_52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case AF9033_TUNER_IT9135_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) len = ARRAY_SIZE(tuner_init_it9135_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) init = tuner_init_it9135_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case AF9033_TUNER_IT9135_61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) len = ARRAY_SIZE(tuner_init_it9135_61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) init = tuner_init_it9135_61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case AF9033_TUNER_IT9135_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) len = ARRAY_SIZE(tuner_init_it9135_62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) init = tuner_init_it9135_62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev->cfg.tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = af9033_wr_reg_val_tab(dev, init, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (dev->cfg.tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case AF9033_TUNER_IT9135_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case AF9033_TUNER_IT9135_61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case AF9033_TUNER_IT9135_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = regmap_write(dev->regmap, 0x800000, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev->bandwidth_hz = 0; /* Force to program all parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Init stats here in order signal app which stats are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) c->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) c->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int af9033_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = regmap_write(dev->regmap, 0x80004c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regmap_write(dev->regmap, 0x800000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 5000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Prevent current leak by setting TS interface to parallel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Enable parallel TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int af9033_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct dvb_frontend_tune_settings *fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* 800 => 2000 because IT9135 v2 is slow to gain lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fesettings->min_delay_ms = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int af9033_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int utmp, adc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 tmp, buf[3], bandwidth_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) c->frequency, c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Check bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bandwidth_reg_val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bandwidth_reg_val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bandwidth_reg_val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(&client->dev, "invalid bandwidth_hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Program tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (c->bandwidth_hz != dev->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (coeff_lut[i].clock == dev->cfg.clock &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (i == ARRAY_SIZE(coeff_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "Couldn't find config for clock %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev->cfg.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) sizeof(coeff_lut[i].val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* IF frequency control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (c->bandwidth_hz != dev->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (clock_adc_lut[i].clock == dev->cfg.clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (i == ARRAY_SIZE(clock_adc_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "Couldn't find ADC clock for clock %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev->cfg.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) adc_freq = clock_adc_lut[i].adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) adc_freq = 2 * adc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Get used IF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (fe->ops.tuner_ops.get_if_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) adc_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!dev->cfg.spec_inv && if_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) utmp = 0x800000 - utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) buf[0] = (utmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) buf[1] = (utmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) buf[2] = (utmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev->bandwidth_hz = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bandwidth_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = regmap_write(dev->regmap, 0x800040, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = regmap_write(dev->regmap, 0x800047, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (c->frequency <= 230000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tmp = 0x00; /* VHF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tmp = 0x01; /* UHF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = regmap_write(dev->regmap, 0x80004b, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Reset FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = regmap_write(dev->regmap, 0x800000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int af9033_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Read all needed TPS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) switch ((buf[0] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) c->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch ((buf[1] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) c->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) switch ((buf[2] >> 0) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) c->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) c->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) c->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) switch ((buf[3] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) c->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) c->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) c->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) switch ((buf[4] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) c->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) c->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) c->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch ((buf[6] >> 0) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) c->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) c->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) c->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) c->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) c->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) c->code_rate_HP = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) switch ((buf[7] >> 0) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) c->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) c->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) c->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) c->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) c->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) c->code_rate_LP = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int ret, tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int utmp, utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = regmap_read(dev->regmap, 0x800047, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Has signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (utmp == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (utmp != 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* TPS lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if ((utmp >> 0) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Full lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = regmap_read(dev->regmap, 0x80f999, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if ((utmp >> 0) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) FE_HAS_VITERBI | FE_HAS_SYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev->fe_status = *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (dev->fe_status & FE_HAS_SIGNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (dev->is_af9035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = regmap_read(dev->regmap, 0x80004a, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tmp = -utmp * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tmp = (utmp - 100) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) c->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) c->strength.stat[0].svalue = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* CNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (dev->fe_status & FE_HAS_VITERBI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Read raw SNR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Read superframe number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (utmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) utmp1 /= utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Read current transmission mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = regmap_read(dev->regmap, 0x80f900, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) switch ((utmp >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* 2k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) utmp1 *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) utmp1 *= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) utmp1 *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) utmp1 *= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Read current modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = regmap_read(dev->regmap, 0x80f903, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) switch ((utmp >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * QPSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * value [653799, 1689999], 2.6 / 13 = 3355443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) utmp1 = clamp(utmp1, 653799U, 1689999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) utmp1 = ((u64)(intlog10(utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) - intlog10(1690000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) + 3355443) * 13 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * QAM-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * value [371105, 827999], 15.7 / 6 = 43900382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) utmp1 = clamp(utmp1, 371105U, 827999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) utmp1 = ((u64)(intlog10(utmp1 - 370000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) - intlog10(828000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) + 43900382) * 6 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * QAM-64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * value [193246, 424999], 23.8 / 8 = 49912218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) utmp1 = clamp(utmp1, 193246U, 424999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) utmp1 = ((u64)(intlog10(utmp1 - 193000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) - intlog10(425000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) + 49912218) * 8 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) utmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_dbg(&client->dev, "cnr=%u\n", utmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) c->cnr.stat[0].svalue = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* UCB/PER/BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (dev->fe_status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Outer FEC, 204 byte packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u16 abort_packet_count, rsd_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Inner FEC, bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 rsd_bit_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Packet count used for measurement is 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * (rsd_packet_count). Maybe it should be increased?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev->error_block_count += abort_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev->total_block_count += rsd_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev->post_bit_error += rsd_bit_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev->post_bit_count += rsd_packet_count * 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) c->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) c->block_count.stat[0].uvalue = dev->total_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) c->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) c->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) c->block_error.stat[0].uvalue = dev->error_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Use DVBv5 CNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (dev->is_af9035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* 1000x => 10x (0.1 dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *snr = div_s64(c->cnr.stat[0].svalue, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* 1000x => 1x (1 dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *snr = div_s64(c->cnr.stat[0].svalue, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Read current modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = regmap_read(dev->regmap, 0x80f903, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* scale value to 0x0000-0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) switch ((utmp >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *snr = *snr * 0xffff / 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *snr = *snr * 0xffff / 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) *snr = *snr * 0xffff / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int ret, tmp, power_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u8 gain_offset, buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (dev->is_af9035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Read signal strength of 0-100 scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = regmap_read(dev->regmap, 0x800048, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Scale value to 0x0000-0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *strength = utmp * 0xffff / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (c->frequency <= 300000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) gain_offset = 7; /* VHF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) gain_offset = 4; /* UHF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) power_real = (utmp - 100 - gain_offset) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (power_real < -15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) else if ((power_real >= -15) && (power_real < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) tmp = (2 * (power_real + 15)) / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else if ((power_real >= 0) && (power_real < 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) tmp = 4 * power_real + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) else if ((power_real >= 20) && (power_real < 35))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tmp = (2 * (power_real - 20)) / 3 + 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tmp = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Scale value to 0x0000-0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) *strength = tmp * 0xffff / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *ber = (dev->post_bit_error - dev->post_bit_error_prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev->post_bit_error_prev = dev->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) *ucblocks = dev->error_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_dbg(&client->dev, "enable=%d\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_dbg(&client->dev, "onoff=%d\n", onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct af9033_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) index, pid, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (pid > 0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = regmap_write(dev->regmap, 0x80f994, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = regmap_write(dev->regmap, 0x80f995, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const struct dvb_frontend_ops af9033_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .delsys = {SYS_DVBT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .name = "Afatech AF9033 (DVB-T)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .frequency_stepsize_hz = 250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .caps = FE_CAN_FEC_1_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) FE_CAN_FEC_5_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) FE_CAN_QAM_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) FE_CAN_HIERARCHY_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .init = af9033_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .sleep = af9033_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .get_tune_settings = af9033_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .set_frontend = af9033_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .get_frontend = af9033_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .read_status = af9033_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .read_snr = af9033_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .read_signal_strength = af9033_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .read_ber = af9033_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .read_ucblocks = af9033_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int af9033_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct af9033_config *cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct af9033_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u8 buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .reg_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) switch (dev->cfg.ts_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case AF9033_TS_MODE_PARALLEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev->ts_mode_parallel = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case AF9033_TS_MODE_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev->ts_mode_serial = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case AF9033_TS_MODE_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* USB mode for AF9035 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (dev->cfg.clock != 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev->cfg.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Create regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev->regmap = regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) switch (dev->cfg.tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case AF9033_TUNER_IT9135_38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case AF9033_TUNER_IT9135_51:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case AF9033_TUNER_IT9135_52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case AF9033_TUNER_IT9135_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case AF9033_TUNER_IT9135_61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case AF9033_TUNER_IT9135_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dev->is_it9135 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) reg = 0x004bfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev->is_af9035 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) reg = 0x0083e9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) buf[0], buf[1], buf[2], buf[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) buf[4], buf[5], buf[6], buf[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Sleep as chip seems to be partly active by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* IT9135 did not like to sleep at that early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (dev->is_af9035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = regmap_write(dev->regmap, 0x80004c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = regmap_write(dev->regmap, 0x800000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Create dvb frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev->fe.demodulator_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) *cfg->fe = &dev->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (cfg->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cfg->ops->pid_filter = af9033_pid_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) cfg->regmap = dev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) err_regmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int af9033_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct af9033_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static const struct i2c_device_id af9033_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {"af9033", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MODULE_DEVICE_TABLE(i2c, af9033_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static struct i2c_driver af9033_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .name = "af9033",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .probe = af9033_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .remove = af9033_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .id_table = af9033_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) module_i2c_driver(af9033_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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