^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Afatech AF9013 demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thanks to Afatech who kindly provided information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "af9013_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct af9013_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct dvb_frontend fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 ts_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 ts_output_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 api_version[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 gpio[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum fe_status fe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* RF and IF AGC limits used for signal strength calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 strength_en, rf_agc_50, rf_agc_80, if_agc_50, if_agc_80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long set_frontend_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long read_status_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long strength_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long cnr_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long ber_ucb_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u16 dvbv3_snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 dvbv3_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 dvbv3_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 dvbv3_ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool first_tune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dev_dbg(&client->dev, "gpio %u, gpioval %02x\n", gpio, gpioval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * GPIO0 & GPIO1 0xd735
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * GPIO2 & GPIO3 0xd736
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) addr = 0xd735;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) addr = 0xd736;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pos = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regmap_update_bits(state->regmap, addr, 0x0f << pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) gpioval << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int af9013_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct dvb_frontend_tune_settings *fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) fesettings->min_delay_ms = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int af9013_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret, i, sampling_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool auto_mode, spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 if_frequency, freq_cw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_dbg(&client->dev, "frequency %u, bandwidth_hz %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) c->frequency, c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* program tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* program CFOE coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (c->bandwidth_hz != state->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (coeff_lut[i].clock == state->clk &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Return an error if can't find bandwidth or the right clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (i == ARRAY_SIZE(coeff_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = regmap_bulk_write(state->regmap, 0xae00, coeff_lut[i].val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sizeof(coeff_lut[i].val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* program frequency control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* get used IF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (fe->ops.tuner_ops.get_if_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = fe->ops.tuner_ops.get_if_frequency(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &if_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if_frequency = state->if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_dbg(&client->dev, "if_frequency %u\n", if_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sampling_freq = if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) while (sampling_freq > (state->clk / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sampling_freq -= state->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (sampling_freq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sampling_freq *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spec_inv = state->spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spec_inv = !state->spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) freq_cw = DIV_ROUND_CLOSEST_ULL((u64)sampling_freq * 0x800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) state->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (spec_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) freq_cw = 0x800000 - freq_cw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) buf[0] = (freq_cw >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) buf[1] = (freq_cw >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) buf[2] = (freq_cw >> 16) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) freq_cw = 0x800000 - freq_cw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) buf[3] = (freq_cw >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) buf[4] = (freq_cw >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) buf[5] = (freq_cw >> 16) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_bulk_write(state->regmap, 0xd140, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = regmap_bulk_write(state->regmap, 0x9be7, buf, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* clear TPS lock flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = regmap_update_bits(state->regmap, 0xd330, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* clear MPEG2 lock flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = regmap_update_bits(state->regmap, 0xd507, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* empty channel function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = regmap_update_bits(state->regmap, 0x9bfe, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* empty DVB-T channel function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = regmap_update_bits(state->regmap, 0x9bc2, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* transmission parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) auto_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) memset(buf, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (c->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case TRANSMISSION_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) buf[0] |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(&client->dev, "invalid transmission_mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) switch (c->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case GUARD_INTERVAL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) buf[0] |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) buf[0] |= (2 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) buf[0] |= (3 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_dbg(&client->dev, "invalid guard_interval\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) switch (c->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case HIERARCHY_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case HIERARCHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) buf[0] |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) buf[0] |= (2 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) buf[0] |= (3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(&client->dev, "invalid hierarchy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) switch (c->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) buf[1] |= (1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) buf[1] |= (2 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_dbg(&client->dev, "invalid modulation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Use HP. How and which case we can switch to LP? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) buf[1] |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (c->code_rate_HP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) buf[2] |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) buf[2] |= (2 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) buf[2] |= (3 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) buf[2] |= (4 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(&client->dev, "invalid code_rate_HP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (c->code_rate_LP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) buf[2] |= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) buf[2] |= (2 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buf[2] |= (3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf[2] |= (4 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case FEC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(&client->dev, "invalid code_rate_LP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) auto_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) buf[1] |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) buf[1] |= (2 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(&client->dev, "invalid bandwidth_hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = regmap_bulk_write(state->regmap, 0xd3c0, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (auto_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* clear easy mode flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = regmap_write(state->regmap, 0xaefd, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_dbg(&client->dev, "auto params\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* set easy mode flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = regmap_write(state->regmap, 0xaefd, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = regmap_write(state->regmap, 0xaefe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(&client->dev, "manual params\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Reset FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = regmap_write(state->regmap, 0xffff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) state->bandwidth_hz = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) state->set_frontend_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) state->first_tune = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int af9013_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = regmap_bulk_read(state->regmap, 0xd3c0, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch ((buf[1] >> 6) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) c->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) c->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) c->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch ((buf[0] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) c->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch ((buf[0] >> 2) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) c->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) switch ((buf[0] >> 4) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) c->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) c->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) c->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) switch ((buf[2] >> 0) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) c->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) c->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) c->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) c->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) c->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch ((buf[2] >> 3) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) c->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) c->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) c->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) c->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch ((buf[1] >> 2) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) c->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) c->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) c->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int af9013_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int ret, stmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int utmp, utmp1, utmp2, utmp3, utmp4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Return status from the cache if it is younger than 2000ms with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * exception of last tune is done during 4000ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (time_is_after_jiffies(state->read_status_jiffies + msecs_to_jiffies(2000)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) time_is_before_jiffies(state->set_frontend_jiffies + msecs_to_jiffies(4000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *status = state->fe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* MPEG2 lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = regmap_read(state->regmap, 0xd507, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if ((utmp >> 6) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* TPS lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = regmap_read(state->regmap, 0xd330, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if ((utmp >> 3) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) utmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_dbg(&client->dev, "fe_status %02x\n", utmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) state->read_status_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) state->fe_status = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *status = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (state->strength_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Check if we support signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = regmap_read(state->regmap, 0x9bee, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if ((utmp >> 0) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Read agc values for signal strength estimation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = regmap_read(state->regmap, 0x9bbd, &utmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = regmap_read(state->regmap, 0x9bd0, &utmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = regmap_read(state->regmap, 0x9be2, &utmp3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = regmap_read(state->regmap, 0x9be4, &utmp4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) state->rf_agc_50 = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) state->rf_agc_80 = utmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) state->if_agc_50 = utmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) state->if_agc_80 = utmp4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "rf_agc_50 %u, rf_agc_80 %u, if_agc_50 %u, if_agc_80 %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) utmp1, utmp2, utmp3, utmp4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) state->strength_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Signal strength is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) state->strength_en = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (time_is_after_jiffies(state->strength_jiffies + msecs_to_jiffies(2000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = regmap_bulk_read(state->regmap, 0xd07c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Construct line equation from tuner dependent -80/-50 dBm agc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * limits and use it to map current agc value to dBm estimate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define agc_gain (buf[0] + buf[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define agc_gain_50dbm (state->rf_agc_50 + state->if_agc_50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define agc_gain_80dbm (state->rf_agc_80 + state->if_agc_80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) stmp1 = 30000 * (agc_gain - agc_gain_80dbm) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) (agc_gain_50dbm - agc_gain_80dbm) - 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "strength %d, agc_gain %d, agc_gain_50dbm %d, agc_gain_80dbm %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) stmp1, agc_gain, agc_gain_50dbm, agc_gain_80dbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) state->strength_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Convert [-90, -30] dBm to [0x0000, 0xffff] for dvbv3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) utmp1 = clamp(stmp1 + 90000, 0, 60000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) state->dvbv3_strength = div_u64((u64)utmp1 * 0xffff, 60000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) c->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) c->strength.stat[0].svalue = stmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* CNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) switch (state->fe_status & FE_HAS_VITERBI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case FE_HAS_VITERBI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (time_is_after_jiffies(state->cnr_jiffies + msecs_to_jiffies(2000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Check if cnr ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = regmap_read(state->regmap, 0xd2e1, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!((utmp >> 3) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_dbg(&client->dev, "cnr not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = regmap_bulk_read(state->regmap, 0xd2e3, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Read current modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = regmap_read(state->regmap, 0xd3c1, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch ((utmp >> 6) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * QPSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * value [653799, 1689999], 2.6 / 13 = 3355443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) utmp1 = clamp(utmp1, 653799U, 1689999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) utmp1 = ((u64)(intlog10(utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) - intlog10(1690000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) + 3355443) * 13 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * QAM-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * value [371105, 827999], 15.7 / 6 = 43900382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) utmp1 = clamp(utmp1, 371105U, 827999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) utmp1 = ((u64)(intlog10(utmp1 - 370000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) - intlog10(828000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) + 43900382) * 6 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * QAM-64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * value [193246, 424999], 23.8 / 8 = 49912218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) utmp1 = clamp(utmp1, 193246U, 424999U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) utmp1 = ((u64)(intlog10(utmp1 - 193000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) - intlog10(425000 - utmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) + 49912218) * 8 * 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(&client->dev, "invalid modulation %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) (utmp >> 6) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) utmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_dbg(&client->dev, "cnr %u\n", utmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) state->cnr_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) state->dvbv3_snr = utmp1 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) c->cnr.stat[0].svalue = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* BER / PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (state->fe_status & FE_HAS_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case FE_HAS_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (time_is_after_jiffies(state->ber_ucb_jiffies + msecs_to_jiffies(2000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Check if ber / ucb is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = regmap_read(state->regmap, 0xd391, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!((utmp >> 4) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_dbg(&client->dev, "ber not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = regmap_bulk_read(state->regmap, 0xd385, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) utmp1 = buf[4] << 16 | buf[3] << 8 | buf[2] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) utmp2 = (buf[1] << 8 | buf[0] << 0) * 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) utmp3 = buf[6] << 8 | buf[5] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) utmp4 = buf[1] << 8 | buf[0] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Use 10000 TS packets for measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (utmp4 != 10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) buf[0] = (10000 >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) buf[1] = (10000 >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = regmap_bulk_write(state->regmap, 0xd385, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Reset ber / ucb counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = regmap_update_bits(state->regmap, 0xd391, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_dbg(&client->dev, "post_bit_error %u, post_bit_count %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) utmp1, utmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_dbg(&client->dev, "block_error %u, block_count %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) utmp3, utmp4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) state->ber_ucb_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) state->dvbv3_ber = utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) state->dvbv3_ucblocks += utmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) c->post_bit_error.stat[0].uvalue += utmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) c->post_bit_count.stat[0].uvalue += utmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) c->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) c->block_error.stat[0].uvalue += utmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) c->block_count.stat[0].uvalue += utmp4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *snr = state->dvbv3_snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) *strength = state->dvbv3_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *ber = state->dvbv3_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) *ucblocks = state->dvbv3_ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int af9013_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int ret, i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) const struct af9013_reg_mask_val *tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* ADC on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = regmap_update_bits(state->regmap, 0xd73a, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Clear reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = regmap_update_bits(state->regmap, 0xd417, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Disable reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* write API version to firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = regmap_bulk_write(state->regmap, 0x9bf2, state->api_version, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* program ADC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) switch (state->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case 28800000: /* 28.800 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) utmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case 20480000: /* 20.480 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) utmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case 28000000: /* 28.000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) utmp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case 25000000: /* 25.000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) utmp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = regmap_update_bits(state->regmap, 0x9bd2, 0x0f, utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) utmp = div_u64((u64)state->clk * 0x80000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) buf[0] = (utmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) buf[1] = (utmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) buf[2] = (utmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = regmap_bulk_write(state->regmap, 0xd180, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Demod core settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_dbg(&client->dev, "load demod core settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) len = ARRAY_SIZE(demod_init_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) tab = demod_init_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tab[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Demod tuner specific settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_dbg(&client->dev, "load tuner specific settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) switch (state->tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case AF9013_TUNER_MXL5003D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) len = ARRAY_SIZE(tuner_init_tab_mxl5003d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) tab = tuner_init_tab_mxl5003d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case AF9013_TUNER_MXL5005D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case AF9013_TUNER_MXL5005R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case AF9013_TUNER_MXL5007T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) len = ARRAY_SIZE(tuner_init_tab_mxl5005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tab = tuner_init_tab_mxl5005;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case AF9013_TUNER_ENV77H11D5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) len = ARRAY_SIZE(tuner_init_tab_env77h11d5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) tab = tuner_init_tab_env77h11d5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case AF9013_TUNER_MT2060:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) len = ARRAY_SIZE(tuner_init_tab_mt2060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) tab = tuner_init_tab_mt2060;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case AF9013_TUNER_MC44S803:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) len = ARRAY_SIZE(tuner_init_tab_mc44s803);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) tab = tuner_init_tab_mc44s803;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case AF9013_TUNER_QT1010:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case AF9013_TUNER_QT1010A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) len = ARRAY_SIZE(tuner_init_tab_qt1010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) tab = tuner_init_tab_qt1010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case AF9013_TUNER_MT2060_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) len = ARRAY_SIZE(tuner_init_tab_mt2060_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) tab = tuner_init_tab_mt2060_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case AF9013_TUNER_TDA18271:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case AF9013_TUNER_TDA18218:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) len = ARRAY_SIZE(tuner_init_tab_tda18271);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) tab = tuner_init_tab_tda18271;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case AF9013_TUNER_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) len = ARRAY_SIZE(tuner_init_tab_unknown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) tab = tuner_init_tab_unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) tab[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* TS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (state->ts_output_pin == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) utmp = 1 << 3 | state->ts_mode << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) utmp = 0 << 3 | state->ts_mode << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = regmap_update_bits(state->regmap, 0xd500, 0x0e, utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* enable lock led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) state->first_tune = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int af9013_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* disable lock led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Enable reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Start reset execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = regmap_write(state->regmap, 0xaeff, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Wait reset performs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = regmap_read_poll_timeout(state->regmap, 0xd417, utmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) (utmp >> 1) & 0x01, 5000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (!((utmp >> 1) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* ADC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = regmap_update_bits(state->regmap, 0xd73a, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct dvb_frontend_ops af9013_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int af9013_download_firmware(struct af9013_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int ret, i, len, rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) u16 checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) const struct firmware *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) const char *name = AF9013_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Check whether firmware is already running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = regmap_read(state->regmap, 0x98be, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dev_dbg(&client->dev, "firmware status %02x\n", utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (utmp == 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dev_info(&client->dev, "found a '%s' in cold state, will try to load a firmware\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) af9013_ops.info.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* Request the firmware, will block and timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = request_firmware(&firmware, name, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev_info(&client->dev, "firmware file '%s' not found %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dev_info(&client->dev, "downloading firmware from file '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Write firmware checksum & size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) for (i = 0; i < firmware->size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) checksum += firmware->data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) buf[0] = (checksum >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) buf[1] = (checksum >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) buf[2] = (firmware->size >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) buf[3] = (firmware->size >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = regmap_bulk_write(state->regmap, 0x50fc, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto err_release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Download firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define LEN_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) for (rem = firmware->size; rem > 0; rem -= LEN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) len = min(LEN_MAX, rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = regmap_bulk_write(state->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) 0x5100 + firmware->size - rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) &firmware->data[firmware->size - rem],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_err(&client->dev, "firmware download failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) goto err_release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) release_firmware(firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Boot firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ret = regmap_write(state->regmap, 0xe205, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* Check firmware status. 0c=OK, 04=fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = regmap_read_poll_timeout(state->regmap, 0x98be, utmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) (utmp == 0x0c || utmp == 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) 5000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev_dbg(&client->dev, "firmware status %02x\n", utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (utmp == 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev_err(&client->dev, "firmware did not run\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) } else if (utmp != 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev_err(&client->dev, "firmware boot timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev_info(&client->dev, "found a '%s' in warm state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) af9013_ops.info.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) err_release_firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) release_firmware(firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct dvb_frontend_ops af9013_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .name = "Afatech AF9013",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .frequency_stepsize_hz = 250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .caps = FE_CAN_FEC_1_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) FE_CAN_FEC_5_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) FE_CAN_QAM_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) FE_CAN_HIERARCHY_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .init = af9013_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .sleep = af9013_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .get_tune_settings = af9013_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .set_frontend = af9013_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .get_frontend = af9013_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .read_status = af9013_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .read_snr = af9013_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .read_signal_strength = af9013_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .read_ber = af9013_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .read_ucblocks = af9013_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int af9013_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_dbg(&client->dev, "onoff %d\n", onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = regmap_update_bits(state->regmap, 0xd503, 0x01, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static int af9013_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct af9013_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_dbg(&client->dev, "index %d, pid %04x, onoff %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) index, pid, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (pid > 0x1fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* 0x2000 is kernel virtual pid for whole ts (all pids) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) buf[0] = (pid >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) buf[1] = (pid >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = regmap_bulk_write(state->regmap, 0xd505, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = regmap_write(state->regmap, 0xd504, onoff << 5 | index << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static struct dvb_frontend *af9013_get_dvb_frontend(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct af9013_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static struct i2c_adapter *af9013_get_i2c_adapter(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct af9013_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return state->muxc->adapter[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * XXX: Hackish solution. We use virtual register, reg bit 16, to carry info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * about i2c adapter locking. Own locking is needed because i2c mux call has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * already locked i2c adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int af9013_select(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct af9013_state *state = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (state->ts_mode == AF9013_TS_MODE_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = regmap_update_bits(state->regmap, 0x1d417, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = regmap_update_bits(state->regmap, 0x1d607, 0x04, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int af9013_deselect(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct af9013_state *state = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct i2c_client *client = state->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (state->ts_mode == AF9013_TS_MODE_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = regmap_update_bits(state->regmap, 0x1d417, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret = regmap_update_bits(state->regmap, 0x1d607, 0x04, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* Own I2C access routines needed for regmap as chip uses extra command byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static int af9013_wregs(struct i2c_client *client, u8 cmd, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) const u8 *val, int len, u8 lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u8 buf[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct i2c_msg msg[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .len = 3 + len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (3 + len > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) buf[0] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) buf[1] = (reg >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) buf[2] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) memcpy(&buf[3], val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ret = __i2c_transfer(client->adapter, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) } else if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int af9013_rregs(struct i2c_client *client, u8 cmd, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) u8 *val, int len, u8 lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .buf = val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) buf[0] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) buf[1] = (reg >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) buf[2] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = __i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) } else if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int af9013_regmap_write(void *context, const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct i2c_client *client = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct af9013_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) u8 lock = !((u8 *)data)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) u16 reg = ((u8 *)data)[1] << 8 | ((u8 *)data)[2] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u8 *val = &((u8 *)data)[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) const unsigned int len = count - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) cmd = 0 << 7|0 << 6|(len - 1) << 2|1 << 1|1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = af9013_wregs(client, cmd, reg, val, len, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) } else if (reg >= 0x5100 && reg < 0x8fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Firmware download */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) cmd = 1 << 7|1 << 6|(len - 1) << 2|1 << 1|1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = af9013_wregs(client, cmd, reg, val, len, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) cmd = 0 << 7|0 << 6|(1 - 1) << 2|1 << 1|1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ret = af9013_wregs(client, cmd, reg + i, val + i, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int af9013_regmap_read(void *context, const void *reg_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) size_t reg_size, void *val_buf, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct i2c_client *client = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct af9013_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u8 lock = !((u8 *)reg_buf)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u16 reg = ((u8 *)reg_buf)[1] << 8 | ((u8 *)reg_buf)[2] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u8 *val = &((u8 *)val_buf)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) const unsigned int len = val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) cmd = 0 << 7|0 << 6|(len - 1) << 2|1 << 1|0 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = af9013_rregs(client, cmd, reg, val_buf, len, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) cmd = 0 << 7|0 << 6|(1 - 1) << 2|1 << 1|0 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = af9013_rregs(client, cmd, reg + i, val + i, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static int af9013_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct af9013_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct af9013_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct dtv_frontend_properties *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 firmware_version[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static const struct regmap_bus regmap_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .read = af9013_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .write = af9013_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* Actual reg is 16 bits, see i2c adapter lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .reg_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) state->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) i2c_set_clientdata(client, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) state->clk = pdata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) state->tuner = pdata->tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) state->if_frequency = pdata->if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) state->ts_mode = pdata->ts_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) state->ts_output_pin = pdata->ts_output_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) state->spec_inv = pdata->spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) memcpy(&state->api_version, pdata->api_version, sizeof(state->api_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) memcpy(&state->gpio, pdata->gpio, sizeof(state->gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) state->regmap = regmap_init(&client->dev, ®map_bus, client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (IS_ERR(state->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = PTR_ERR(state->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* Create mux i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) state->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) af9013_select, af9013_deselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!state->muxc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) state->muxc->priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Download firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (state->ts_mode != AF9013_TS_MODE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ret = af9013_download_firmware(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) goto err_i2c_mux_del_adapters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* Firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = regmap_bulk_read(state->regmap, 0x5103, firmware_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) sizeof(firmware_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) goto err_i2c_mux_del_adapters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Set GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) for (i = 0; i < sizeof(state->gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ret = af9013_set_gpio(state, i, state->gpio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) goto err_i2c_mux_del_adapters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Create dvb frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) memcpy(&state->fe.ops, &af9013_ops, sizeof(state->fe.ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* Setup callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pdata->get_dvb_frontend = af9013_get_dvb_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pdata->get_i2c_adapter = af9013_get_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pdata->pid_filter = af9013_pid_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pdata->pid_filter_ctrl = af9013_pid_filter_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* Init stats to indicate which stats are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) c = &state->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) c->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) c->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_info(&client->dev, "Afatech AF9013 successfully attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_info(&client->dev, "firmware version: %d.%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) firmware_version[0], firmware_version[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) firmware_version[2], firmware_version[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) err_i2c_mux_del_adapters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) i2c_mux_del_adapters(state->muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) err_regmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) regmap_exit(state->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dev_dbg(&client->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static int af9013_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct af9013_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) i2c_mux_del_adapters(state->muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) regmap_exit(state->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const struct i2c_device_id af9013_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {"af9013", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) MODULE_DEVICE_TABLE(i2c, af9013_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static struct i2c_driver af9013_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .name = "af9013",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .probe = af9013_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .remove = af9013_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .id_table = af9013_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) module_i2c_driver(af9013_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) MODULE_DESCRIPTION("Afatech AF9013 DVB-T demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) MODULE_FIRMWARE(AF9013_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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