^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * flexcop-reg.h - register abstraction for FlexCopII, FlexCopIIb and FlexCopIII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * see flexcop.c for copyright information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __FLEXCOP_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __FLEXCOP_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) FLEXCOP_UNK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) FLEXCOP_II,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) FLEXCOP_IIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) FLEXCOP_III,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) } flexcop_revision_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) FC_UNK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) FC_CABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) FC_AIR_DVBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) FC_AIR_ATSC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) FC_AIR_ATSC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FC_AIR_ATSC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FC_SKY_REV23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FC_SKY_REV26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FC_SKY_REV27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FC_SKY_REV28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FC_SKYS2_REV33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } flexcop_device_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FC_USB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FC_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) } flexcop_bus_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* FlexCop IBI Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "flexcop_ibi_value_le.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "flexcop_ibi_value_be.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #error no endian defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define fc_data_Tag_ID_DVB 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define fc_data_Tag_ID_ATSC 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define fc_data_Tag_ID_IDSB 0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define fc_key_code_default 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define fc_key_code_even 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define fc_key_code_odd 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern flexcop_ibi_value ibi_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FC_I2C_PORT_DEMOD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FC_I2C_PORT_EEPROM = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FC_I2C_PORT_TUNER = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } flexcop_i2c_port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FC_WRITE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FC_READ = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } flexcop_access_op_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FC_SRAM_DEST_NET = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FC_SRAM_DEST_CAI = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FC_SRAM_DEST_CAO = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FC_SRAM_DEST_MEDIA = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) } flexcop_sram_dest_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FC_SRAM_DEST_TARGET_WAN_USB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FC_SRAM_DEST_TARGET_DMA1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FC_SRAM_DEST_TARGET_DMA2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FC_SRAM_DEST_TARGET_FC3_CA = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } flexcop_sram_dest_target_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FC_SRAM_2_32KB = 0, /* 64KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FC_SRAM_1_32KB = 1, /* 32KB - default fow FCII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FC_SRAM_1_128KB = 2, /* 128KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FC_SRAM_1_48KB = 3, /* 48KB - default for FCIII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } flexcop_sram_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FC_WAN_SPEED_4MBITS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FC_WAN_SPEED_8MBITS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FC_WAN_SPEED_12MBITS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FC_WAN_SPEED_16MBITS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } flexcop_wan_speed_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FC_DMA_1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FC_DMA_2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } flexcop_dma_index_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FC_DMA_SUBADDR_0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FC_DMA_SUBADDR_1 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } flexcop_dma_addr_index_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* names of the particular registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma1_000 = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dma1_004 = 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dma1_008 = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma1_00c = 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dma2_010 = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dma2_014 = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dma2_018 = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma2_01c = 0x01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tw_sm_c_100 = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tw_sm_c_104 = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tw_sm_c_108 = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tw_sm_c_10c = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tw_sm_c_110 = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) lnb_switch_freq_200 = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) misc_204 = 0x204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ctrl_208 = 0x208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irq_20c = 0x20c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sw_reset_210 = 0x210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) misc_214 = 0x214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mbox_v8_to_host_218 = 0x218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mbox_host_to_v8_21c = 0x21c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pid_filter_300 = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pid_filter_304 = 0x304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pid_filter_308 = 0x308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pid_filter_30c = 0x30c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) index_reg_310 = 0x310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pid_n_reg_314 = 0x314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mac_low_reg_318 = 0x318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mac_high_reg_31c = 0x31c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data_tag_400 = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) card_id_408 = 0x408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) card_id_40c = 0x40c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mac_address_418 = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mac_address_41c = 0x41c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ci_600 = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pi_604 = 0x604,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pi_608 = 0x608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dvb_reg_60c = 0x60c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sram_ctrl_reg_700 = 0x700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) net_buf_reg_704 = 0x704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cai_buf_reg_708 = 0x708,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cao_buf_reg_70c = 0x70c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) media_buf_reg_710 = 0x710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sram_dest_reg_714 = 0x714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) net_buf_reg_718 = 0x718,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) wan_ctrl_reg_71c = 0x71c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } flexcop_ibi_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define flexcop_set_ibi_value(reg,attr,val) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) v.reg.attr = val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) fc->write_ibi_reg(fc,reg,v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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