Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * flexcop-i2c.c - flexcop internal 2Wire bus (I2C) and dvb i2c initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * see flexcop.c for copyright information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include "flexcop.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define FC_MAX_I2C_RETRIES 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) static int flexcop_i2c_operation(struct flexcop_device *fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 		flexcop_ibi_value *r100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	flexcop_ibi_value r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	r100->tw_sm_c_100.working_start = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	deb_i2c("r100 before: %08x\n",r100->raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	fc->write_ibi_reg(fc, tw_sm_c_100, ibi_zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	fc->write_ibi_reg(fc, tw_sm_c_100, *r100); /* initiating i2c operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	for (i = 0; i < FC_MAX_I2C_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		r = fc->read_ibi_reg(fc, tw_sm_c_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		if (!r.tw_sm_c_100.no_base_addr_ack_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			if (r.tw_sm_c_100.st_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 				*r100 = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 				deb_i2c("i2c success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			deb_i2c("suffering from an i2c ack_error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	deb_i2c("tried %d times i2c operation, never finished or too many ack errors.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int flexcop_i2c_read4(struct flexcop_i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		flexcop_ibi_value r100, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	flexcop_ibi_value r104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	int len = r100.tw_sm_c_100.total_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		/* remember total_bytes is buflen-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* work-around to have CableStar2 and SkyStar2 rev 2.7 work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * correctly:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * the ITD1000 is behind an i2c-gate which closes automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * after an i2c-transaction the STV0297 needs 2 consecutive reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * one with no_base_addr = 0 and one with 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * those two work-arounds are conflictin: we check for the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * type, it is set when probing the ITD1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (i2c->fc->dev_type == FC_SKY_REV27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		r100.tw_sm_c_100.no_base_addr_ack_error = i2c->no_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ret = flexcop_i2c_operation(i2c->fc, &r100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		deb_i2c("Retrying operation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		r100.tw_sm_c_100.no_base_addr_ack_error = i2c->no_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		ret = flexcop_i2c_operation(i2c->fc, &r100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		deb_i2c("read failed. %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	buf[0] = r100.tw_sm_c_100.data1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		r104 = i2c->fc->read_ibi_reg(i2c->fc, tw_sm_c_104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		deb_i2c("read: r100: %08x, r104: %08x\n", r100.raw, r104.raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		/* there is at least one more byte, otherwise we wouldn't be here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		buf[1] = r104.tw_sm_c_104.data2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (len > 1) buf[2] = r104.tw_sm_c_104.data3_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (len > 2) buf[3] = r104.tw_sm_c_104.data4_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int flexcop_i2c_write4(struct flexcop_device *fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		flexcop_ibi_value r100, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	flexcop_ibi_value r104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int len = r100.tw_sm_c_100.total_bytes; /* remember total_bytes is buflen-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	r104.raw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* there is at least one byte, otherwise we wouldn't be here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	r100.tw_sm_c_100.data1_reg = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	r104.tw_sm_c_104.data2_reg = len > 0 ? buf[1] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	r104.tw_sm_c_104.data3_reg = len > 1 ? buf[2] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	r104.tw_sm_c_104.data4_reg = len > 2 ? buf[3] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	deb_i2c("write: r100: %08x, r104: %08x\n", r100.raw, r104.raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* write the additional i2c data before doing the actual i2c operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	fc->write_ibi_reg(fc, tw_sm_c_104, r104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return flexcop_i2c_operation(fc, &r100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int flexcop_i2c_request(struct flexcop_i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			flexcop_access_op_t op, u8 chipaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			u8 start_addr, u8 *buf, u16 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int len = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u8 addr = start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u16 bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	flexcop_ibi_value r100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	deb_i2c("port %d %s(%02x): register %02x, size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		i2c->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		op == FC_READ ? "rd" : "wr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		chipaddr, start_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	r100.raw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	r100.tw_sm_c_100.chipaddr = chipaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	r100.tw_sm_c_100.twoWS_rw = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	r100.tw_sm_c_100.twoWS_port_reg = i2c->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* in that case addr is the only value ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * we write it twice as baseaddr and val0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * BBTI is doing it like that for ISL6421 at least */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (i2c->no_base_addr && len == 0 && op == FC_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		buf = &start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	while (len != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		bytes_to_transfer = len > 4 ? 4 : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		r100.tw_sm_c_100.total_bytes = bytes_to_transfer - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		r100.tw_sm_c_100.baseaddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (op == FC_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			ret = flexcop_i2c_read4(i2c, r100, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			ret = flexcop_i2c_write4(i2c->fc, r100, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		p  += bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		addr += bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		len  -= bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	deb_i2c_dump("port %d %s(%02x): register %02x: %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		i2c->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		op == FC_READ ? "rd" : "wr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		chipaddr, start_addr, size, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* exported for PCI i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EXPORT_SYMBOL(flexcop_i2c_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* master xfer callback for demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int flexcop_master_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct flexcop_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Some drivers use 1 byte or 0 byte reads as probes, which this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * driver doesn't support.  These probes will always fail, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * hack makes them always succeed.  If one knew how, it would of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * course be better to actually do the read.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (num == 1 && msgs[0].flags == I2C_M_RD && msgs[0].len <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (mutex_lock_interruptible(&i2c->fc->i2c_mutex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		/* reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (i+1 < num && (msgs[i+1].flags == I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			ret = i2c->fc->i2c_request(i2c, FC_READ, msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					msgs[i].buf[0], msgs[i+1].buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					msgs[i+1].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			i++; /* skip the following message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		} else /* writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			ret = i2c->fc->i2c_request(i2c, FC_WRITE, msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					msgs[i].buf[0], &msgs[i].buf[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					msgs[i].len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			deb_i2c("i2c master_xfer failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mutex_unlock(&i2c->fc->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static u32 flexcop_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct i2c_algorithm flexcop_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.master_xfer	= flexcop_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.functionality	= flexcop_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int flexcop_i2c_init(struct flexcop_device *fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	mutex_init(&fc->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	fc->fc_i2c_adap[0].fc = fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	fc->fc_i2c_adap[1].fc = fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	fc->fc_i2c_adap[2].fc = fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	fc->fc_i2c_adap[0].port = FC_I2C_PORT_DEMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	fc->fc_i2c_adap[1].port = FC_I2C_PORT_EEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	fc->fc_i2c_adap[2].port = FC_I2C_PORT_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	strscpy(fc->fc_i2c_adap[0].i2c_adap.name, "B2C2 FlexCop I2C to demod",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		sizeof(fc->fc_i2c_adap[0].i2c_adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	strscpy(fc->fc_i2c_adap[1].i2c_adap.name, "B2C2 FlexCop I2C to eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		sizeof(fc->fc_i2c_adap[1].i2c_adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	strscpy(fc->fc_i2c_adap[2].i2c_adap.name, "B2C2 FlexCop I2C to tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		sizeof(fc->fc_i2c_adap[2].i2c_adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	i2c_set_adapdata(&fc->fc_i2c_adap[0].i2c_adap, &fc->fc_i2c_adap[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	i2c_set_adapdata(&fc->fc_i2c_adap[1].i2c_adap, &fc->fc_i2c_adap[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	i2c_set_adapdata(&fc->fc_i2c_adap[2].i2c_adap, &fc->fc_i2c_adap[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	fc->fc_i2c_adap[0].i2c_adap.algo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		fc->fc_i2c_adap[1].i2c_adap.algo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		fc->fc_i2c_adap[2].i2c_adap.algo = &flexcop_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	fc->fc_i2c_adap[0].i2c_adap.algo_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		fc->fc_i2c_adap[1].i2c_adap.algo_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		fc->fc_i2c_adap[2].i2c_adap.algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	fc->fc_i2c_adap[0].i2c_adap.dev.parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		fc->fc_i2c_adap[1].i2c_adap.dev.parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		fc->fc_i2c_adap[2].i2c_adap.dev.parent = fc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ret = i2c_add_adapter(&fc->fc_i2c_adap[0].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = i2c_add_adapter(&fc->fc_i2c_adap[1].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		goto adap_1_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = i2c_add_adapter(&fc->fc_i2c_adap[2].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		goto adap_2_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	fc->init_state |= FC_STATE_I2C_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) adap_2_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	i2c_del_adapter(&fc->fc_i2c_adap[1].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) adap_1_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	i2c_del_adapter(&fc->fc_i2c_adap[0].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void flexcop_i2c_exit(struct flexcop_device *fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (fc->init_state & FC_STATE_I2C_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		i2c_del_adapter(&fc->fc_i2c_adap[2].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		i2c_del_adapter(&fc->fc_i2c_adap[1].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		i2c_del_adapter(&fc->fc_i2c_adap[0].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	fc->init_state &= ~FC_STATE_I2C_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }