^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MCB_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MCB_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PCI_VENDOR_ID_MEN 0x1a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CHAMELEONV2_MAGIC 0xabce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CHAM_HEADER_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum chameleon_descriptor_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) CHAMELEON_DTYPE_GENERAL = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CHAMELEON_DTYPE_BRIDGE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CHAMELEON_DTYPE_CPU = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CHAMELEON_DTYPE_BAR = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) CHAMELEON_DTYPE_END = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum chameleon_bus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CHAMELEON_BUS_WISHBONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CHAMELEON_BUS_AVALON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CHAMELEON_BUS_LPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CHAMELEON_BUS_ISA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * struct chameleon_fpga_header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @revision: Revison of Chameleon table in FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @model: Chameleon table model ASCII char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @minor: Revision minor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @magic: Chameleon header magic number (0xabce for version 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @reserved: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @filename: Filename of FPGA bitstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct chameleon_fpga_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* This one has no '\0' at the end!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) char filename[CHAMELEON_FILENAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HEADER_MAGIC_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * struct chameleon_gdd - Chameleon General Device Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @irq: the position in the FPGA's IRQ controller vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @rev: the revision of the variant's implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @var: the variant of the IP core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @dev: the device the IP core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @dtype: device descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @bar: BAR offset that must be added to module offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @inst: the instance number of the device, 0 is first instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @group: the group the device belongs to (0 = no group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @reserved: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @offset: beginning of the address window of desired module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @size: size of the module's address window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct chameleon_gdd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le32 reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le32 reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __le32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* GDD Register 1 fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GDD_IRQ(x) ((x) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GDD_REV(x) (((x) >> 5) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GDD_VAR(x) (((x) >> 11) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GDD_DEV(x) (((x) >> 18) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GDD_DTY(x) (((x) >> 28) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* GDD Register 2 fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GDD_BAR(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GDD_INS(x) (((x) >> 3) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GDD_GRP(x) (((x) >> 9) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * struct chameleon_bdd - Chameleon Bridge Device Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @irq: the position in the FPGA's IRQ controller vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @rev: the revision of the variant's implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @var: the variant of the IP core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @dev: the device the IP core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @dtype: device descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @bar: BAR offset that must be added to module offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @inst: the instance number of the device, 0 is first instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @dbar: destination bar from the bus _behind_ the bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @chamoff: offset within the BAR of the source bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct chameleon_bdd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int irq:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int rev:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int var:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int dev:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int dtype:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int bar:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int inst:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int dbar:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int group:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int reserved:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 chamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct chameleon_bar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BAR_CNT(x) ((x) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CHAMELEON_BAR_MAX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BAR_DESC_SIZE(x) ((x) * sizeof(struct chameleon_bar) + sizeof(__le32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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