^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/mailbox/tegra186-hsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mailbox.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HSP_INT_IE(x) (0x100 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HSP_INT_IV 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HSP_INT_IR 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HSP_INT_EMPTY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HSP_INT_EMPTY_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSP_INT_FULL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HSP_INT_FULL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HSP_INT_DIMENSIONING 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HSP_nSM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HSP_nSS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HSP_nAS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HSP_nDB_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HSP_nSI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HSP_nINT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HSP_DB_TRIGGER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HSP_DB_ENABLE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HSP_DB_RAW 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSP_DB_PENDING 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HSP_SM_SHRD_MBOX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HSP_SM_SHRD_MBOX_FULL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HSP_DB_CCPLEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HSP_DB_BPMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HSP_DB_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct tegra_hsp_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tegra_hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct tegra_hsp_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tegra_hsp *hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct tegra_hsp_doorbell {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct tegra_hsp_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tegra_hsp_mailbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tegra_hsp_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool producer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra_hsp_db_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct tegra_hsp_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct tegra_hsp_db_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool has_per_mb_ie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct tegra_hsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct tegra_hsp_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mbox_controller mbox_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mbox_controller mbox_sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int doorbell_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int *shared_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int shared_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int num_sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int num_as;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int num_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int num_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int num_si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct list_head doorbells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct tegra_hsp_mailbox *mailboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return readl(hsp->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(value, hsp->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return readl(channel->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(value, channel->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct tegra_hsp_doorbell *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tegra_hsp_doorbell *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) list_for_each_entry(entry, &hsp->doorbells, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (entry->master == master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct tegra_hsp_doorbell *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) db = __tegra_hsp_doorbell_get(hsp, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct tegra_hsp *hsp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long master, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock(&hsp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) db = __tegra_hsp_doorbell_get(hsp, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Depending on the bootloader chain, the CCPLEX doorbell will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * have some doorbells enabled, which means that requesting an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * interrupt will immediately fire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * In that case, db->channel.chan will still be NULL here and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * cause a crash if not properly guarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * It remains to be seen if ignoring the doorbell in that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * is the correct solution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (db && db->channel.chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mbox_chan_received_data(db->channel.chan, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock(&hsp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct tegra_hsp *hsp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long bit, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 status, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* process EMPTY interrupts first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for_each_set_bit(bit, &mask, hsp->num_sm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (mb->producer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Disable EMPTY interrupts until data is sent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * the next message. These interrupts are level-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * triggered, so if we kept them enabled they would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * constantly trigger until we next write data into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * the message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock(&hsp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tegra_hsp_writel(hsp, hsp->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) HSP_INT_IE(hsp->shared_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_unlock(&hsp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mbox_chan_txdone(mb->channel.chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* process FULL interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for_each_set_bit(bit, &mask, hsp->num_sm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!mb->producer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) value = tegra_hsp_channel_readl(&mb->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) HSP_SM_SHRD_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) value &= ~HSP_SM_SHRD_MBOX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msg = (void *)(unsigned long)value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mbox_chan_received_data(mb->channel.chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Need to clear all bits here since some producers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * such as TCU, depend on fields in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * getting cleared by the consumer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * The mailbox API doesn't give the consumers a way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * of doing that explicitly, so we have to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * we cover all possible cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tegra_hsp_channel_writel(&mb->channel, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) HSP_SM_SHRD_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct tegra_hsp_channel *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int master, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) offset += index * 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) db->channel.regs = hsp->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) db->channel.hsp = hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) db->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) db->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) list_add_tail(&db->list, &hsp->doorbells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return &db->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct tegra_hsp_doorbell *db = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct tegra_hsp_doorbell *db = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct tegra_hsp *hsp = db->channel.hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct tegra_hsp_doorbell *ccplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (db->master >= chan->mbox->num_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(chan->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "invalid master ID %u for HSP channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) db->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!ccplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * On simulation platforms the BPMP hasn't had a chance yet to mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * the doorbell as ringable by the CCPLEX, so we want to skip extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * checks here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) value |= BIT(db->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct tegra_hsp_doorbell *db = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct tegra_hsp *hsp = db->channel.hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct tegra_hsp_doorbell *ccplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!ccplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) value &= ~BIT(db->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct mbox_chan_ops tegra_hsp_db_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .send_data = tegra_hsp_doorbell_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .startup = tegra_hsp_doorbell_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .shutdown = tegra_hsp_doorbell_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct tegra_hsp_mailbox *mb = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct tegra_hsp *hsp = mb->channel.hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (WARN_ON(!mb->producer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* copy data and mark mailbox full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) value = (u32)(unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) value |= HSP_SM_SHRD_MBOX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* enable EMPTY interrupt for the shared mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct tegra_hsp_mailbox *mb = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct tegra_hsp_channel *ch = &mb->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) timeout = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mbox_chan_txdone(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Wait until channel is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (chan->active_req != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct tegra_hsp_mailbox *mb = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct tegra_hsp_channel *ch = &mb->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct tegra_hsp *hsp = mb->channel.hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) chan->txdone_method = TXDONE_BY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * Shared mailboxes start out as consumers by default. FULL and EMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * interrupts are coalesced at the same shared interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Keep EMPTY interrupts disabled at startup and only enable them when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * the mailbox is actually full. This is required because the FULL and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * enabled all the time would cause an interrupt storm while mailboxes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * are idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (mb->producer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (hsp->soc->has_per_mb_ie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (mb->producer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tegra_hsp_channel_writel(ch, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tegra_hsp_channel_writel(ch, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) HSP_SM_SHRD_MBOX_FULL_INT_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct tegra_hsp_mailbox *mb = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct tegra_hsp_channel *ch = &mb->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct tegra_hsp *hsp = mb->channel.hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (hsp->soc->has_per_mb_ie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (mb->producer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tegra_hsp_channel_writel(ch, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tegra_hsp_channel_writel(ch, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) HSP_SM_SHRD_MBOX_FULL_INT_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (mb->producer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct mbox_chan_ops tegra_hsp_sm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .send_data = tegra_hsp_mailbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .flush = tegra_hsp_mailbox_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .startup = tegra_hsp_mailbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .shutdown = tegra_hsp_mailbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) const struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int type = args->args[0], master = args->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) db = tegra_hsp_doorbell_get(hsp, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) channel = &db->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (IS_ERR(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ERR_CAST(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_lock_irqsave(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) for (i = 0; i < mbox->num_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) chan = &mbox->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!chan->con_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) channel->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) chan->con_priv = db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spin_unlock_irqrestore(&hsp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return chan ?: ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int type = args->args[0], index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct tegra_hsp_mailbox *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) index = args->args[1] & TEGRA_HSP_SM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) index >= hsp->num_sm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mb = &hsp->mailboxes[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mb->producer = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mb->producer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return mb->channel.chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct tegra_hsp_db_map *map = hsp->soc->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct tegra_hsp_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) while (map->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) channel = tegra_hsp_doorbell_create(hsp, map->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) map->master, map->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (IS_ERR(channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!hsp->mailboxes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for (i = 0; i < hsp->num_sm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mb->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mb->channel.hsp = hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mb->channel.chan = &hsp->mbox_sm.chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mb->channel.chan->con_priv = mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int i, irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (i = 0; i < hsp->num_si; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) irq = hsp->shared_irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_name(hsp->dev), hsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(hsp->dev, "failed to request interrupt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hsp->shared_irq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (i == hsp->num_si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(hsp->dev, "failed to find available interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int tegra_hsp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct tegra_hsp *hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!hsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hsp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hsp->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) INIT_LIST_HEAD(&hsp->doorbells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) spin_lock_init(&hsp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hsp->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (IS_ERR(hsp->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return PTR_ERR(hsp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) err = platform_get_irq_byname_optional(pdev, "doorbell");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) hsp->doorbell_irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (hsp->num_si > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sizeof(*hsp->shared_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!hsp->shared_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) for (i = 0; i < hsp->num_si; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) name = kasprintf(GFP_KERNEL, "shared%u", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err = platform_get_irq_byname_optional(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hsp->shared_irqs[i] = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) devm_kfree(&pdev->dev, hsp->shared_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) hsp->shared_irqs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* setup the doorbell controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hsp->mbox_db.num_chans = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hsp->mbox_db.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hsp->mbox_db.ops = &tegra_hsp_db_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sizeof(*hsp->mbox_db.chans),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!hsp->mbox_db.chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (hsp->doorbell_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err = tegra_hsp_add_doorbells(hsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(&pdev->dev, "failed to add doorbells: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* setup the shared mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) hsp->mbox_sm.num_chans = hsp->num_sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) hsp->mbox_sm.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sizeof(*hsp->mbox_sm.chans),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (!hsp->mbox_sm.chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (hsp->shared_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) platform_set_drvdata(pdev, hsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (hsp->doorbell_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_name(&pdev->dev), hsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "failed to request doorbell IRQ#%u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) hsp->doorbell_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (hsp->shared_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) err = tegra_hsp_request_shared_irq(hsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int __maybe_unused tegra_hsp_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct tegra_hsp *hsp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct tegra_hsp_doorbell *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) list_for_each_entry(db, &hsp->doorbells, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (db && db->channel.chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) tegra_hsp_doorbell_startup(db->channel.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (hsp->mailboxes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for (i = 0; i < hsp->num_sm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (mb->channel.chan->cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) tegra_hsp_mailbox_startup(mb->channel.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct dev_pm_ops tegra_hsp_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .resume_noirq = tegra_hsp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct tegra_hsp_soc tegra186_hsp_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .map = tegra186_hsp_db_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .has_per_mb_ie = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct tegra_hsp_soc tegra194_hsp_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .map = tegra186_hsp_db_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .has_per_mb_ie = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct of_device_id tegra_hsp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct platform_driver tegra_hsp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "tegra-hsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .of_match_table = tegra_hsp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .pm = &tegra_hsp_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .probe = tegra_hsp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int __init tegra_hsp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return platform_driver_register(&tegra_hsp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) core_initcall(tegra_hsp_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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