^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Spreadtrum mailbox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_MBOX_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_MBOX_MSG_LOW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_MBOX_MSG_HIGH 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_MBOX_TRIGGER 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_MBOX_FIFO_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_MBOX_FIFO_STS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_MBOX_IRQ_STS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_MBOX_IRQ_MSK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_MBOX_LOCK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_MBOX_FIFO_DEPTH 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Bit and mask definiation for inbox's SPRD_MBOX_FIFO_STS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_INBOX_FIFO_DELIVER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Bit and mask definiation for SPRD_MBOX_IRQ_STS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_MBOX_IRQ_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Bit and mask definiation for outbox's SPRD_MBOX_FIFO_STS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_OUTBOX_FIFO_FULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_OUTBOX_FIFO_WR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_OUTBOX_FIFO_RD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Bit and mask definiation for inbox's SPRD_MBOX_IRQ_MSK register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPRD_INBOX_FIFO_BLOCK_IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPRD_INBOX_FIFO_OVERFLOW_IRQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_INBOX_FIFO_DELIVER_IRQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Bit and mask definiation for outbox's SPRD_MBOX_IRQ_MSK register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_MBOX_CHAN_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sprd_mbox_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *inbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *outbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 outbox_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mbox_chan chan[SPRD_MBOX_CHAN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct sprd_mbox_priv *to_sprd_mbox_priv(struct mbox_controller *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return container_of(mbox, struct sprd_mbox_priv, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u32 sprd_mbox_get_fifo_len(struct sprd_mbox_priv *priv, u32 fifo_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 wr_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_WR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SPRD_OUTBOX_FIFO_POS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 rd_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_RD_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SPRD_OUTBOX_FIFO_POS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * If the read pointer is equal with write pointer, which means the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * is full or empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (wr_pos == rd_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (fifo_sts & SPRD_OUTBOX_FIFO_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) fifo_len = priv->outbox_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) fifo_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } else if (wr_pos > rd_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) fifo_len = wr_pos - rd_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) fifo_len = priv->outbox_fifo_depth - rd_pos + wr_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static irqreturn_t sprd_mbox_outbox_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sprd_mbox_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 fifo_sts, fifo_len, msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int i, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fifo_sts = readl(priv->outbox_base + SPRD_MBOX_FIFO_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) fifo_len = sprd_mbox_get_fifo_len(priv, fifo_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!fifo_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_warn_ratelimited(priv->dev, "spurious outbox interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for (i = 0; i < fifo_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) msg[0] = readl(priv->outbox_base + SPRD_MBOX_MSG_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) msg[1] = readl(priv->outbox_base + SPRD_MBOX_MSG_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) id = readl(priv->outbox_base + SPRD_MBOX_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) chan = &priv->chan[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (chan->cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mbox_chan_received_data(chan, (void *)msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_warn_ratelimited(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "message's been dropped at ch[%d]\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Trigger to update outbox FIFO pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(0x1, priv->outbox_base + SPRD_MBOX_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Clear irq status after reading all message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(SPRD_MBOX_IRQ_CLR, priv->outbox_base + SPRD_MBOX_IRQ_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static irqreturn_t sprd_mbox_inbox_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct sprd_mbox_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 fifo_sts, send_sts, busy, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fifo_sts = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Get the inbox data delivery status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) send_sts = (fifo_sts & SPRD_INBOX_FIFO_DELIVER_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SPRD_INBOX_FIFO_DELIVER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!send_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_warn_ratelimited(priv->dev, "spurious inbox interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) while (send_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) id = __ffs(send_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) send_sts &= (send_sts - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) chan = &priv->chan[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Check if the message was fetched by remote traget, if yes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * that means the transmission has been completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) busy = fifo_sts & SPRD_INBOX_FIFO_BUSY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!(busy & BIT(id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mbox_chan_txdone(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Clear FIFO delivery and overflow status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel(fifo_sts &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (SPRD_INBOX_FIFO_DELIVER_MASK | SPRD_INBOX_FIFO_OVERLOW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) priv->inbox_base + SPRD_MBOX_FIFO_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Clear irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(SPRD_MBOX_IRQ_CLR, priv->inbox_base + SPRD_MBOX_IRQ_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int sprd_mbox_send_data(struct mbox_chan *chan, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long id = (unsigned long)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 *data = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Write data into inbox FIFO, and only support 8 bytes every time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(data[0], priv->inbox_base + SPRD_MBOX_MSG_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(data[1], priv->inbox_base + SPRD_MBOX_MSG_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Set target core id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(id, priv->inbox_base + SPRD_MBOX_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Trigger remote request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(0x1, priv->inbox_base + SPRD_MBOX_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int sprd_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long id = (unsigned long)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) timeout = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) busy = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SPRD_INBOX_FIFO_BUSY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!(busy & BIT(id))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mbox_chan_txdone(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sprd_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (priv->refcnt++ == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Select outbox FIFO mode and reset the outbox FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel(0x0, priv->outbox_base + SPRD_MBOX_FIFO_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Enable inbox FIFO overflow and delivery interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val = readl(priv->inbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val &= ~(SPRD_INBOX_FIFO_OVERFLOW_IRQ | SPRD_INBOX_FIFO_DELIVER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Enable outbox FIFO not empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val = readl(priv->outbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void sprd_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (--priv->refcnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Disable inbox & outbox interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct mbox_chan_ops sprd_mbox_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .send_data = sprd_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .flush = sprd_mbox_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .startup = sprd_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .shutdown = sprd_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void sprd_mbox_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct sprd_mbox_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int sprd_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sprd_mbox_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret, inbox_irq, outbox_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * The Spreadtrum mailbox uses an inbox to send messages to the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * core, and uses an outbox to receive messages from other cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Thus the mailbox controller supplies 2 different register addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * and IRQ numbers for inbox and outbox.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) priv->inbox_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (IS_ERR(priv->inbox_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return PTR_ERR(priv->inbox_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) priv->outbox_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (IS_ERR(priv->outbox_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return PTR_ERR(priv->outbox_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) priv->clk = devm_clk_get(dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "failed to get mailbox clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = devm_add_action_or_reset(dev, sprd_mbox_disable, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(dev, "failed to add mailbox disable action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) inbox_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (inbox_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return inbox_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = devm_request_irq(dev, inbox_irq, sprd_mbox_inbox_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) IRQF_NO_SUSPEND, dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(dev, "failed to request inbox IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) outbox_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (outbox_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return outbox_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = devm_request_irq(dev, outbox_irq, sprd_mbox_outbox_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) IRQF_NO_SUSPEND, dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Get the default outbox FIFO depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) priv->outbox_fifo_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) readl(priv->outbox_base + SPRD_MBOX_FIFO_DEPTH) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) priv->mbox.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) priv->mbox.chans = &priv->chan[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) priv->mbox.num_chans = SPRD_MBOX_CHAN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) priv->mbox.ops = &sprd_mbox_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) priv->mbox.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) for (id = 0; id < SPRD_MBOX_CHAN_MAX; id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) priv->chan[id].con_priv = (void *)id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = devm_mbox_controller_register(dev, &priv->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(dev, "failed to register mailbox: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct of_device_id sprd_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .compatible = "sprd,sc9860-mailbox", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(of, sprd_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct platform_driver sprd_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .name = "sprd-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .of_match_table = sprd_mbox_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .probe = sprd_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) module_platform_driver(sprd_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_AUTHOR("Baolin Wang <baolin.wang@unisoc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DESCRIPTION("Spreadtrum mailbox driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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