Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <soc/rockchip/rockchip-mailbox.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MAILBOX_A2B_INTEN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAILBOX_A2B_STATUS		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAILBOX_B2A_INTEN		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAILBOX_B2A_STATUS		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct rockchip_mbox_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct rockchip_mbox_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct rockchip_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	void __iomem *mbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	spinlock_t cfg_lock; /* Serialise access to the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct rockchip_mbox_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct rockchip_mbox_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct rockchip_mbox_msg *msg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct rockchip_mbox_chan *chans = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (status & (1U << chans->idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		dev_err(mb->mbox.dev, "The mailbox channel is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		chans->idx, msg->cmd, msg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writel_relaxed(msg->data, mb->mbox_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		       MAILBOX_A2B_DAT(chans->idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int rockchip_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct rockchip_mbox_chan *chans = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 val = 0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Enable the corresponding B2A interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spin_lock(&mb->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		(1U << chans->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	spin_unlock(&mb->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void rockchip_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct rockchip_mbox_chan *chans = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 val = 0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Disable the corresponding B2A interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	spin_lock(&mb->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		~(1U << chans->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_unlock(&mb->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.send_data	= rockchip_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.startup	= rockchip_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.shutdown	= rockchip_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int rockchip_mbox_read_msg(struct mbox_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			   struct rockchip_mbox_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct rockchip_mbox *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct rockchip_mbox_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (!chan || !msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	chans = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	msg->cmd  = mb->msg[chans->idx].cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	msg->data = mb->msg[chans->idx].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXPORT_SYMBOL_GPL(rockchip_mbox_read_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct rockchip_mbox_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if ((status & (1U << idx)) && irq == mb->chans[idx].irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			/* Get cmd/data from the channel of B2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			msg = &mb->msg[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			msg->cmd = readl_relaxed(mb->mbox_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 						 MAILBOX_B2A_CMD(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			msg->data = readl_relaxed(mb->mbox_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 						  MAILBOX_B2A_DAT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				idx, msg->cmd, msg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			if (mb->mbox.chans[idx].cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				mbox_chan_received_data(&mb->mbox.chans[idx], msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			/* Clear mbox interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			writel_relaxed(1U << idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				       mb->mbox_base + MAILBOX_B2A_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct rockchip_mbox_data rk3368_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.num_chans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct of_device_id rockchip_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_DEVICE_TABLE(of, rockchip_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int rockchip_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct rockchip_mbox *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	const struct rockchip_mbox_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret, irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	drv_data = (const struct rockchip_mbox_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mb->msg = devm_kcalloc(&pdev->dev, drv_data->num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			       sizeof(*mb->msg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!mb->msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				 sizeof(*mb->chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (!mb->chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				      sizeof(*mb->mbox.chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!mb->mbox.chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	platform_set_drvdata(pdev, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mb->mbox.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mb->mbox.num_chans = drv_data->num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	mb->mbox.ops = &rockchip_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	mb->mbox.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	spin_lock_init(&mb->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(mb->mbox_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return PTR_ERR(mb->mbox_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (IS_ERR(mb->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		ret = PTR_ERR(mb->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ret = clk_prepare_enable(mb->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	for (i = 0; i < mb->mbox.num_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			/* For shared irq case, only could be got one time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			if (i > 0 && irq == -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				mb->chans[i].irq = mb->chans[0].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			mb->chans[i].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		mb->chans[i].idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		mb->mbox.chans[i].con_priv = &mb->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	for (i = 0; i < mb->mbox.num_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		/* For shared irq case, only request irq thread one time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if (i > 0 && mb->chans[i].irq == mb->chans[0].irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = devm_request_threaded_irq(&pdev->dev, mb->chans[i].irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 						NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 						rockchip_mbox_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 						IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 						dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 						mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		if (device_property_present(&pdev->dev, "wakeup-source"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			enable_irq_wake(mb->chans[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	clk_disable_unprepare(mb->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct platform_driver rockchip_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.probe	= rockchip_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.name = "rockchip-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.of_match_table = of_match_ptr(rockchip_mbox_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #if defined(CONFIG_ROCKCHIP_THUNDER_BOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int __init rockchip_mbox_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return platform_driver_register(&rockchip_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) core_initcall(rockchip_mbox_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) module_platform_driver(rockchip_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");