Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <soc/rockchip/rk3368-mailbox.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <soc/rockchip/scpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAILBOX_VERSION			"V1.00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAILBOX_A2B_INTEN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAILBOX_A2B_STATUS		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MAILBOX_B2A_INTEN		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MAILBOX_B2A_STATUS		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MAILBOX_ATOMIC_LOCK(x)		(0x100 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* A2B: 0 - 2k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define A2B_BUF(size, idx)		((idx) * (size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* B2A: 2k - 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define B2A_BUF(size, idx)		(((idx) + 4) * (size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct rk3368_mbox_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct rk3368_mbox_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct rk3368_mbox_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct rk3368_mbox *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct rk3368_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	void __iomem *mbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* The base address of share memory to transfer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem *buf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* The maximum size of buf for each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct rk3368_mbox_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MBOX_CHAN_NUMS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) int idx_map_irq[MBOX_CHAN_NUMS] = {0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static inline int chan_to_idx(struct rk3368_mbox *mb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			      struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return (chan - mb->mbox.chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int rk3368_mbox_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct rk3368_mbox *mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct rk3368_mbox_msg *msg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int idx = chan_to_idx(mb, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if ((msg->tx_size > mb->buf_size) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	    (msg->rx_size > mb->buf_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			mb->buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		idx, msg->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mb->chans[idx].msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (msg->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		memcpy(mb->buf_base + A2B_BUF(mb->buf_size, idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		       msg->tx_buf, msg->tx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	writel_relaxed(msg->rx_size, mb->mbox_base + MAILBOX_A2B_DAT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int rk3368_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void rk3368_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct rk3368_mbox *mb = dev_get_drvdata(chan->mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int idx = chan_to_idx(mb, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mb->chans[idx].msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct mbox_chan_ops rk3368_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.send_data	= rk3368_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.startup	= rk3368_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.shutdown	= rk3368_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static irqreturn_t rk3368_mbox_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct rk3368_mbox *mb = (struct rk3368_mbox *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if ((status & (1 << idx)) && (irq == idx_map_irq[idx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			/* Clear mbox interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			writel_relaxed(1 << idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				       mb->mbox_base + MAILBOX_B2A_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static irqreturn_t rk3368_mbox_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct rk3368_mbox_msg *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct rk3368_mbox *mb = (struct rk3368_mbox *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		if (irq != idx_map_irq[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		msg = mb->chans[idx].msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			dev_err(mb->mbox.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				"Chan[%d]: B2A message is NULL\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			break; /* spurious */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		if (msg->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			memcpy(msg->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			       mb->buf_base + B2A_BUF(mb->buf_size, idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			       msg->rx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		mbox_chan_received_data(&mb->mbox.chans[idx], msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			idx, msg->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct rk3368_mbox_drv_data rk3368_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.num_chans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct of_device_id rk3368_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.compatible = "rockchip,rk3368-mbox-legacy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.data = &rk3368_drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int rk3368_mbox_suspend(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			       pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct rk3368_mbox *mb = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (scpi_sys_set_mcu_state_suspend())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dev_err(mb->mbox.dev, "scpi_sys_set_mcu_state_suspend timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int rk3368_mbox_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct rk3368_mbox *mb = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	writel_relaxed((1 << mb->mbox.num_chans) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		       mb->mbox_base + MAILBOX_B2A_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (scpi_sys_set_mcu_state_resume())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dev_err(mb->mbox.dev, "scpi_sys_set_mcu_state_resume timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int rk3368_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct rk3368_mbox *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	const struct rk3368_mbox_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret, irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dev_info(&pdev->dev, "rk3368-mailbox initialized, version: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		 MAILBOX_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	match = of_match_node(rk3368_mbox_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	drv_data = (const struct rk3368_mbox_drv_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (!mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				 sizeof(*mb->chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!mb->chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				      sizeof(*mb->mbox.chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!mb->mbox.chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	platform_set_drvdata(pdev, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mb->mbox.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mb->mbox.num_chans = drv_data->num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	mb->mbox.ops = &rk3368_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mb->mbox.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!mb->mbox_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Each channel has two buffers for A2B and B2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mb->buf_size = resource_size(res) / (drv_data->num_chans * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mb->buf_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!mb->buf_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (IS_ERR(mb->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ret = PTR_ERR(mb->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ret = clk_prepare_enable(mb->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	for (i = 0; i < mb->mbox.num_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = devm_request_threaded_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 						rk3368_mbox_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 						rk3368_mbox_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						dev_name(&pdev->dev), mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		mb->chans[i].idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		mb->chans[i].mb = mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		mb->chans[i].msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		idx_map_irq[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* Enable all B2A interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	writel_relaxed((1 << mb->mbox.num_chans) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		       mb->mbox_base + MAILBOX_B2A_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ret = mbox_controller_register(&mb->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int rk3368_mbox_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct rk3368_mbox *mb = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	mbox_controller_unregister(&mb->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct platform_driver rk3368_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.probe	= rk3368_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.remove	= rk3368_mbox_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.suspend = rk3368_mbox_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.resume	= rk3368_mbox_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.name = "rk3368-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		.of_match_table = of_match_ptr(rk3368_mbox_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init rk3368_mbox_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return platform_driver_register(&rk3368_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) subsys_initcall(rk3368_mbox_init);