^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/mailbox/qcom-ipcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IPCC_MBOX_MAX_CHAN 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* IPCC Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IPCC_REG_SEND_ID 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IPCC_REG_RECV_ID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IPCC_REG_CLIENT_CLEAR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPCC_CLIENT_ID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPCC_NO_PENDING_IRQ GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * struct qcom_ipcc_chan_info - Per-mailbox-channel info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @client_id: The client-id to which the interrupt has to be triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @signal_id: The signal-id to which the interrupt has to be triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct qcom_ipcc_chan_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 client_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 signal_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct qcom_ipcc - Holder for the mailbox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @dev: Device associated with this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @base: Base address of the IPCC frame associated to APSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @irq_domain: The irq_domain associated with this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @chan: The mailbox channels array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @mchan: The per-mailbox channel info array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @mbox: The mailbox controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @irq: Summary irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct qcom_ipcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mbox_chan chan[IPCC_MBOX_MAX_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct qcom_ipcc_chan_info mchan[IPCC_MBOX_MAX_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return container_of(mbox, struct qcom_ipcc, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct qcom_ipcc *ipcc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (hwirq == IPCC_NO_PENDING_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) virq = irq_find_mapping(ipcc->irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void qcom_ipcc_mask_irq(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct irq_chip qcom_ipcc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "ipcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .irq_mask = qcom_ipcc_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .irq_unmask = qcom_ipcc_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct qcom_ipcc *ipcc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) irq_set_chip_data(irq, ipcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int qcom_ipcc_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device_node *node, const u32 *intspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (intsize != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct irq_domain_ops qcom_ipcc_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .map = qcom_ipcc_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .xlate = qcom_ipcc_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct qcom_ipcc_chan_info *mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chan->con_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct of_phandle_args *ph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct qcom_ipcc_chan_info *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ph->args_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < IPCC_MBOX_MAX_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chan = &ipcc->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!chan->con_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mchan = &ipcc->mchan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mchan->client_id = ph->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mchan->signal_id = ph->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chan->con_priv = mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return chan ?: ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .send_data = qcom_ipcc_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .shutdown = qcom_ipcc_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mbox_controller *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device *dev = ipcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mbox = &ipcc->mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mbox->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mbox->num_chans = IPCC_MBOX_MAX_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mbox->chans = ipcc->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mbox->ops = &ipcc_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mbox->of_xlate = qcom_ipcc_mbox_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mbox->txdone_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mbox->txdone_poll = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return devm_mbox_controller_register(dev, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int qcom_ipcc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct qcom_ipcc *ipcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!ipcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ipcc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ipcc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(ipcc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR(ipcc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ipcc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ipcc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ipcc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) &qcom_ipcc_irq_ops, ipcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!ipcc->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = qcom_ipcc_setup_mbox(ipcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto err_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IRQF_TRIGGER_HIGH, "ipcc", ipcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto err_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enable_irq_wake(ipcc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) platform_set_drvdata(pdev, ipcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err_mbox:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq_domain_remove(ipcc->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int qcom_ipcc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) disable_irq_wake(ipcc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_domain_remove(ipcc->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct of_device_id qcom_ipcc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "qcom,ipcc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct platform_driver qcom_ipcc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .probe = qcom_ipcc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .remove = qcom_ipcc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "qcom-ipcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .of_match_table = qcom_ipcc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int __init qcom_ipcc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return platform_driver_register(&qcom_ipcc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) arch_initcall(qcom_ipcc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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