^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 BayLibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Synchronised with arm_mhu.c from :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jassi Brar <jaswinder.singh@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define INTR_SET_OFS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTR_STAT_OFS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTR_CLR_OFS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MHU_SEC_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MHU_LP_OFFSET 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MHU_HP_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TX_REG_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MHU_CHANS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct platform_mhu_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *tx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *rx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct platform_mhu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct platform_mhu_link mlink[MHU_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mbox_chan chan[MHU_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct mbox_chan *chan = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct platform_mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mbox_chan_received_data(chan, (void *)&val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct platform_mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return (val == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct platform_mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 *arg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int platform_mhu_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct platform_mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) IRQF_SHARED, "platform_mhu_link", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_err(chan->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "Unable to acquire IRQ %d\n", mlink->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void platform_mhu_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct platform_mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) free_irq(mlink->irq, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct mbox_chan_ops platform_mhu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .send_data = platform_mhu_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .startup = platform_mhu_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .shutdown = platform_mhu_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .last_tx_done = platform_mhu_last_tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int platform_mhu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct platform_mhu *mhu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int platform_mhu_reg[MHU_CHANS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Allocate memory for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!mhu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mhu->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(mhu->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return PTR_ERR(mhu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (i = 0; i < MHU_CHANS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mhu->chan[i].con_priv = &mhu->mlink[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mhu->mlink[i].irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (mhu->mlink[i].irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(dev, "failed to get irq%d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return mhu->mlink[i].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mhu->mbox.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mhu->mbox.chans = &mhu->chan[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mhu->mbox.num_chans = MHU_CHANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mhu->mbox.ops = &platform_mhu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mhu->mbox.txdone_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mhu->mbox.txdone_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mhu->mbox.txpoll_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) platform_set_drvdata(pdev, mhu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) err = devm_mbox_controller_register(dev, &mhu->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "Failed to register mailboxes %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_info(dev, "Platform MHU Mailbox registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct of_device_id platform_mhu_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .compatible = "amlogic,meson-gxbb-mhu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct platform_driver platform_mhu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .probe = platform_mhu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "platform-mhu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .of_match_table = platform_mhu_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_platform_driver(platform_mhu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_ALIAS("platform:platform-mhu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_DESCRIPTION("Platform MHU Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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