^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pl320-ipc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IPCMxSOURCE(m) ((m) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IPCMxDSET(m) (((m) * 0x40) + 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IPCMxDCLEAR(m) (((m) * 0x40) + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPCMxDSTATUS(m) (((m) * 0x40) + 0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IPCMxMODE(m) (((m) * 0x40) + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPCMxMSET(m) (((m) * 0x40) + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPCMxMCLEAR(m) (((m) * 0x40) + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPCMxMSTATUS(m) (((m) * 0x40) + 0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IPCMxSEND(m) (((m) * 0x40) + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPCMxDR(m, dr) (((m) * 0x40) + ((dr) * 4) + 0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPCMMIS(irq) (((irq) * 8) + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IPCMRIS(irq) (((irq) * 8) + 0x804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MBOX_MASK(n) (1 << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPC_TX_MBOX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IPC_RX_MBOX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CHAN_MASK(n) (1 << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define A9_SOURCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define M3_SOURCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void __iomem *ipc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int ipc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static DEFINE_MUTEX(ipc_m1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static DECLARE_COMPLETION(ipc_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void set_destination(int source, int mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline void clear_destination(int source, int mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __ipc_send(int mbox, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 __ipc_rcv(int mbox, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* blocking implmentation from the A9 side, not usuable in interrupts! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int pl320_ipc_transmit(u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mutex_lock(&ipc_m1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) init_completion(&ipc_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __ipc_send(IPC_TX_MBOX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = wait_for_completion_timeout(&ipc_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = __ipc_rcv(IPC_TX_MBOX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mutex_unlock(&ipc_m1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static irqreturn_t ipc_handler(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 data[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) complete(&ipc_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __ipc_rcv(IPC_RX_MBOX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int pl320_ipc_register_notifier(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return atomic_notifier_chain_register(&ipc_notifier, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int pl320_ipc_unregister_notifier(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return atomic_notifier_chain_unregister(&ipc_notifier, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ipc_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ipc_irq = adev->irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Init slow mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel_relaxed(CHAN_MASK(A9_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel_relaxed(CHAN_MASK(M3_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ipc_base + IPCMxDSET(IPC_TX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ipc_base + IPCMxMSET(IPC_TX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Init receive mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel_relaxed(CHAN_MASK(M3_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(CHAN_MASK(A9_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ipc_base + IPCMxDSET(IPC_RX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ipc_base + IPCMxMSET(IPC_RX_MBOX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) iounmap(ipc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct amba_id pl320_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .id = 0x00041320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct amba_driver pl320_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "pl320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .id_table = pl320_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .probe = pl320_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init ipc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return amba_driver_register(&pl320_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) subsys_initcall(ipc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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