^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP mailbox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Suman Anna <s-anna@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/omap-mailbox.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "mailbox.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAILBOX_REVISION 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OMAP2_MAILBOX_IRQSTATUS(u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) OMAP2_MAILBOX_IRQENABLE(u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) : OMAP2_MAILBOX_IRQENABLE(u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Interrupt register configuration types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MBOX_INTR_CFG_TYPE1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MBOX_INTR_CFG_TYPE2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct omap_mbox_fifo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long fifo_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long msg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long irqdisable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 intr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct omap_mbox_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct kfifo fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct omap_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct omap_mbox_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct omap_mbox_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mutex cfg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *mbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 *irq_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 num_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 num_fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct omap_mbox **mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct mbox_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct list_head elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct omap_mbox_fifo_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int tx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int tx_usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int rx_usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool send_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct omap_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct omap_mbox_queue *rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct omap_mbox_device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct omap_mbox_fifo tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct omap_mbox_fifo rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool send_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* global variables for the mailbox devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static DEFINE_MUTEX(omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static LIST_HEAD(omap_mbox_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) module_param(mbox_kfifo_size, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!chan || !chan->con_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return (struct omap_mbox *)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return __raw_readl(mdev->mbox_base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __raw_writel(val, mdev->mbox_base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Mailbox FIFO handle functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static u32 mbox_fifo_read(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return mbox_read_reg(mbox->parent, fifo->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mbox_write_reg(mbox->parent, msg, fifo->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int mbox_fifo_empty(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int mbox_fifo_full(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return mbox_read_reg(mbox->parent, fifo->fifo_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Mailbox IRQ handle functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &mbox->tx_fifo : &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 bit = fifo->intr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 irqstatus = fifo->irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mbox_write_reg(mbox->parent, bit, irqstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Flush posted write for irq status to avoid spurious interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mbox_read_reg(mbox->parent, irqstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &mbox->tx_fifo : &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 bit = fifo->intr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 irqenable = fifo->irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 irqstatus = fifo->irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 enable = mbox_read_reg(mbox->parent, irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 status = mbox_read_reg(mbox->parent, irqstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return (int)(enable & status & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &mbox->tx_fifo : &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 bit = fifo->intr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 irqenable = fifo->irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) l = mbox_read_reg(mbox->parent, irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) l |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mbox_write_reg(mbox->parent, l, irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &mbox->tx_fifo : &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 bit = fifo->intr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 irqdisable = fifo->irqdisable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Read and update the interrupt configuration register for pre-OMAP4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * OMAP4 and later SoCs have a dedicated interrupt disabling register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!mbox->intr_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mbox_write_reg(mbox->parent, bit, irqdisable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (WARN_ON(!mbox))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) _omap_mbox_enable_irq(mbox, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL(omap_mbox_enable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (WARN_ON(!mbox))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) _omap_mbox_disable_irq(mbox, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL(omap_mbox_disable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Message receiver(workqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void mbox_rx_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct omap_mbox_queue *mq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) container_of(work, struct omap_mbox_queue, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mbox_msg_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) WARN_ON(len != sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) data = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mbox_chan_received_data(mq->mbox->chan, (void *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_lock_irq(&mq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (mq->full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mq->full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_unlock_irq(&mq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Mailbox interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void __mbox_tx_interrupt(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) _omap_mbox_disable_irq(mbox, IRQ_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ack_mbox_irq(mbox, IRQ_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mbox_chan_txdone(mbox->chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void __mbox_rx_interrupt(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct omap_mbox_queue *mq = mbox->rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) while (!mbox_fifo_empty(mbox)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _omap_mbox_disable_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mq->full = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goto nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) msg = mbox_fifo_read(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WARN_ON(len != sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* no more messages in the fifo. clear IRQ source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ack_mbox_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) nomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) schedule_work(&mbox->rxq->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static irqreturn_t mbox_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct omap_mbox *mbox = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (is_mbox_irq(mbox, IRQ_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __mbox_tx_interrupt(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (is_mbox_irq(mbox, IRQ_RX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __mbox_rx_interrupt(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void (*work)(struct work_struct *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct omap_mbox_queue *mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mq = kzalloc(sizeof(*mq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!mq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spin_lock_init(&mq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) INIT_WORK(&mq->work, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) kfree(mq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void mbox_queue_free(struct omap_mbox_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) kfifo_free(&q->fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) kfree(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int omap_mbox_startup(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct omap_mbox_queue *mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mq = mbox_queue_alloc(mbox, mbox_rx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!mq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mbox->rxq = mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mq->mbox = mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mbox->name, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_err("failed to register mailbox interrupt:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto fail_request_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (mbox->send_no_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mbox->chan->txdone_method = TXDONE_BY_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) _omap_mbox_enable_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fail_request_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mbox_queue_free(mbox->rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void omap_mbox_fini(struct omap_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) _omap_mbox_disable_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) free_irq(mbox->irq, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) flush_work(&mbox->rxq->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mbox_queue_free(mbox->rxq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const char *mbox_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct omap_mbox *_mbox, *mbox = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct omap_mbox **mboxes = mdev->mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!mboxes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (i = 0; (_mbox = mboxes[i]); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!strcmp(_mbox->name, mbox_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mbox = _mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) const char *chan_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device *dev = cl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct omap_mbox *mbox = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct omap_mbox_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mutex_lock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) list_for_each_entry(mdev, &omap_mbox_devices, elem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mbox = omap_mbox_device_find(mdev, chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mutex_unlock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!mbox || !mbox->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) chan = mbox->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chan->msg_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) chan->msg_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chan->active_req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) chan->cl = cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) init_completion(&chan->tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = chan->mbox->ops->startup(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_err("Unable to startup the chan (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mbox_free_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) chan = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) EXPORT_SYMBOL(omap_mbox_request_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static struct class omap_mbox_class = { .name = "mbox", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int omap_mbox_register(struct omap_mbox_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct omap_mbox **mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!mdev || !mdev->mboxes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mboxes = mdev->mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; mboxes[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct omap_mbox *mbox = mboxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mbox->dev = device_create(&omap_mbox_class, mdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0, mbox, "%s", mbox->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (IS_ERR(mbox->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = PTR_ERR(mbox->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mutex_lock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) list_add(&mdev->elem, &omap_mbox_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mutex_unlock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = devm_mbox_controller_register(mdev->dev, &mdev->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) device_unregister(mboxes[i]->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int omap_mbox_unregister(struct omap_mbox_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct omap_mbox **mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!mdev || !mdev->mboxes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_lock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) list_del(&mdev->elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mutex_unlock(&omap_mbox_devices_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mboxes = mdev->mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) for (i = 0; mboxes[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) device_unregister(mboxes[i]->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int omap_mbox_chan_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct omap_mbox_device *mdev = mbox->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_lock(&mdev->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pm_runtime_get_sync(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = omap_mbox_startup(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pm_runtime_put_sync(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_unlock(&mdev->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct omap_mbox_device *mdev = mbox->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mutex_lock(&mdev->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) omap_mbox_fini(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pm_runtime_put_sync(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_unlock(&mdev->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!mbox_fifo_full(mbox)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) _omap_mbox_enable_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mbox_fifo_write(mbox, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) _omap_mbox_disable_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* we must read and ack the interrupt directly from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mbox_fifo_read(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ack_mbox_irq(mbox, IRQ_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!mbox_fifo_full(mbox)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mbox_fifo_write(mbox, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* always enable the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) _omap_mbox_enable_irq(mbox, IRQ_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 msg = omap_mbox_message(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (mbox->send_no_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = omap_mbox_chan_send_noirq(mbox, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = omap_mbox_chan_send(mbox, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct mbox_chan_ops omap_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .startup = omap_mbox_chan_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .send_data = omap_mbox_chan_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .shutdown = omap_mbox_chan_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int omap_mbox_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct omap_mbox_device *mdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 usr, fifo, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (usr = 0; usr < mdev->num_users; usr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int omap_mbox_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct omap_mbox_device *mdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 usr, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (usr = 0; usr < mdev->num_users; usr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct dev_pm_ops omap_mbox_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct of_device_id omap_mailbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .compatible = "ti,omap2-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .data = &omap2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .compatible = "ti,omap3-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .data = &omap2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .compatible = "ti,omap4-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .data = &omap4_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .compatible = "ti,am654-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .data = &omap4_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const struct of_phandle_args *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) phandle phandle = sp->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct omap_mbox_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct omap_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mdev = container_of(controller, struct omap_mbox_device, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (WARN_ON(!mdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) node = of_find_node_by_phandle(phandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pr_err("%s: could not find node phandle 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __func__, phandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mbox = omap_mbox_device_find(mdev, node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return mbox ? mbox->chan : ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int omap_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct mbox_chan *chnls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct omap_mbox **list, *mbox, *mboxblk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct omap_mbox_fifo_info *finfo, *finfoblk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct omap_mbox_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct omap_mbox_fifo *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) const struct omap_mbox_match_data *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 intr_type, info_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 num_users, num_fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 tmp[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pr_err("%s: only DT-based devices are supported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) match_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!match_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) intr_type = match_data->intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) info_count = of_get_available_child_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!info_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_err(&pdev->dev, "no available mbox devices found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!finfoblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) finfo = finfoblk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) for (i = 0; i < info_count; i++, finfo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) child = of_get_next_available_child(node, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ARRAY_SIZE(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) finfo->tx_id = tmp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) finfo->tx_irq = tmp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) finfo->tx_usr = tmp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ARRAY_SIZE(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) finfo->rx_id = tmp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) finfo->rx_irq = tmp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) finfo->rx_usr = tmp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) finfo->name = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (of_find_property(child, "ti,mbox-send-noirq", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) finfo->send_no_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (IS_ERR(mdev->mbox_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return PTR_ERR(mdev->mbox_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!mdev->irq_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* allocate one extra for marking end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!chnls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!mboxblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mbox = mboxblk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) finfo = finfoblk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) for (i = 0; i < info_count; i++, finfo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fifo = &mbox->tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) fifo = &mbox->rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) mbox->send_no_irq = finfo->send_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mbox->intr_type = intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mbox->parent = mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mbox->name = finfo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (mbox->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return mbox->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) mbox->chan = &chnls[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) chnls[i].con_priv = mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) list[i] = mbox++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_init(&mdev->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mdev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) mdev->num_users = num_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mdev->num_fifos = num_fifos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mdev->intr_type = intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mdev->mboxes = list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * IRQ and is needed to run the Tx state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mdev->controller.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mdev->controller.dev = mdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mdev->controller.ops = &omap_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) mdev->controller.chans = chnls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mdev->controller.num_chans = info_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mdev->controller.of_xlate = omap_mbox_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = omap_mbox_register(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) platform_set_drvdata(pdev, mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pm_runtime_enable(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = pm_runtime_get_sync(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pm_runtime_put_noidle(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * just print the raw revision register, the format is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * uniform across all SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) l = mbox_read_reg(mdev, MAILBOX_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = pm_runtime_put_sync(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret < 0 && ret != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) devm_kfree(&pdev->dev, finfoblk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pm_runtime_disable(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) omap_mbox_unregister(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int omap_mbox_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pm_runtime_disable(mdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) omap_mbox_unregister(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct platform_driver omap_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .probe = omap_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .remove = omap_mbox_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "omap-mailbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .pm = &omap_mbox_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .of_match_table = of_match_ptr(omap_mailbox_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int __init omap_mbox_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) err = class_register(&omap_mbox_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* kfifo size sanity check: alignment and minimal size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) err = platform_driver_register(&omap_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) class_unregister(&omap_mbox_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) subsys_initcall(omap_mbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void __exit omap_mbox_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) platform_driver_unregister(&omap_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) class_unregister(&omap_mbox_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) module_exit(omap_mbox_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_AUTHOR("Toshihiro Kobayashi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_AUTHOR("Hiroshi DOYU");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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