Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * APM X-Gene SLIMpro MailBox Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Feng Kan fkan@apm.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MBOX_CON_NAME			"slimpro-mbox"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MBOX_REG_SET_OFFSET		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MBOX_CNT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MBOX_STATUS_AVAIL_MASK		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MBOX_STATUS_ACK_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Configuration and Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_DB_IN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_DB_DIN0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_DB_DIN1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_DB_OUT		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_DB_DOUT0		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_DB_DOUT1		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_DB_STAT		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_DB_STATMASK		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * X-Gene SlimPRO mailbox channel information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @dev:	Device to which it is attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @chan:	Pointer to mailbox communication channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @reg:	Base address to access channel registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @irq:	Interrupt number of the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @rx_msg:	Received message storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct slimpro_mbox_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct mbox_chan	*chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void __iomem		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32			rx_msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * X-Gene SlimPRO Mailbox controller data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * X-Gene SlimPRO Mailbox controller has 8 commnunication channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * Each channel has a separate IRQ number assgined to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @mb_ctrl:	Representation of the commnunication channel controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @mc:		Array of SlimPRO mailbox channels of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @chans:	Array of mailbox communication channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct slimpro_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct mbox_controller		mb_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct slimpro_mbox_chan	mc[MBOX_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct mbox_chan		chans[MBOX_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void mb_chan_send_msg(struct slimpro_mbox_chan *mb_chan, u32 *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writel(msg[1], mb_chan->reg + REG_DB_DOUT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	writel(msg[2], mb_chan->reg + REG_DB_DOUT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writel(msg[0], mb_chan->reg + REG_DB_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void mb_chan_recv_msg(struct slimpro_mbox_chan *mb_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mb_chan->rx_msg[1] = readl(mb_chan->reg + REG_DB_DIN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mb_chan->rx_msg[2] = readl(mb_chan->reg + REG_DB_DIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	mb_chan->rx_msg[0] = readl(mb_chan->reg + REG_DB_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int mb_chan_status_ack(struct slimpro_mbox_chan *mb_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 val = readl(mb_chan->reg + REG_DB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (val & MBOX_STATUS_ACK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		writel(MBOX_STATUS_ACK_MASK, mb_chan->reg + REG_DB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int mb_chan_status_avail(struct slimpro_mbox_chan *mb_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 val = readl(mb_chan->reg + REG_DB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (val & MBOX_STATUS_AVAIL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		mb_chan_recv_msg(mb_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		writel(MBOX_STATUS_AVAIL_MASK, mb_chan->reg + REG_DB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static irqreturn_t slimpro_mbox_irq(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct slimpro_mbox_chan *mb_chan = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (mb_chan_status_ack(mb_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		mbox_chan_txdone(mb_chan->chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (mb_chan_status_avail(mb_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		mbox_chan_received_data(mb_chan->chan, mb_chan->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int slimpro_mbox_send_data(struct mbox_chan *chan, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct slimpro_mbox_chan *mb_chan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mb_chan_send_msg(mb_chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int slimpro_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct slimpro_mbox_chan *mb_chan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	rc = devm_request_irq(mb_chan->dev, mb_chan->irq, slimpro_mbox_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			      MBOX_CON_NAME, mb_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (unlikely(rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		dev_err(mb_chan->dev, "failed to register mailbox interrupt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			mb_chan->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* Enable HW interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	writel(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	       mb_chan->reg + REG_DB_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Unmask doorbell status interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	val = readl(mb_chan->reg + REG_DB_STATMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	val &= ~(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	writel(val, mb_chan->reg + REG_DB_STATMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void slimpro_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct slimpro_mbox_chan *mb_chan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Mask doorbell status interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	val = readl(mb_chan->reg + REG_DB_STATMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	val |= (MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	writel(val, mb_chan->reg + REG_DB_STATMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	devm_free_irq(mb_chan->dev, mb_chan->irq, mb_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct mbox_chan_ops slimpro_mbox_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.send_data = slimpro_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.startup = slimpro_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.shutdown = slimpro_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int slimpro_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct slimpro_mbox *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	void __iomem *mb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ctx = devm_kzalloc(&pdev->dev, sizeof(struct slimpro_mbox), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mb_base = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(mb_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return PTR_ERR(mb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Setup mailbox links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for (i = 0; i < MBOX_CNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ctx->mc[i].irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (ctx->mc[i].irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				dev_err(&pdev->dev, "no available IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			dev_info(&pdev->dev, "no IRQ for channel %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ctx->mc[i].dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ctx->mc[i].reg = mb_base + i * MBOX_REG_SET_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ctx->mc[i].chan = &ctx->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ctx->chans[i].con_priv = &ctx->mc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* Setup mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ctx->mb_ctrl.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ctx->mb_ctrl.chans = ctx->chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ctx->mb_ctrl.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ctx->mb_ctrl.ops = &slimpro_mbox_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ctx->mb_ctrl.num_chans = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	rc = devm_mbox_controller_register(&pdev->dev, &ctx->mb_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			"APM X-Gene SLIMpro MailBox register failed:%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	dev_info(&pdev->dev, "APM X-Gene SLIMpro MailBox registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct of_device_id slimpro_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{.compatible = "apm,xgene-slimpro-mbox" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_DEVICE_TABLE(of, slimpro_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct acpi_device_id slimpro_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{"APMC0D01", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DEVICE_TABLE(acpi, slimpro_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct platform_driver slimpro_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.probe	= slimpro_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.name = "xgene-slimpro-mbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.of_match_table = of_match_ptr(slimpro_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.acpi_match_table = ACPI_PTR(slimpro_acpi_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int __init slimpro_mbox_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return platform_driver_register(&slimpro_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void __exit slimpro_mbox_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	platform_driver_unregister(&slimpro_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) subsys_initcall(slimpro_mbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) module_exit(slimpro_mbox_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_DESCRIPTION("APM X-Gene SLIMpro Mailbox Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_LICENSE("GPL");