Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright Altera Corporation (C) 2013-2014. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DRIVER_NAME	"altera-mailbox"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MAILBOX_CMD_REG			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAILBOX_PTR_REG			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAILBOX_STS_REG			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAILBOX_INTMASK_REG		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define INT_PENDING_MSK			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define INT_SPACE_MSK			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define STS_PENDING_MSK			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define STS_FULL_MSK			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define STS_FULL_OFT			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MBOX_PENDING(status)	(((status) & STS_PENDING_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MBOX_FULL(status)	(((status) & STS_FULL_MSK) >> STS_FULL_OFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) enum altera_mbox_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MBOX_CMD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	MBOX_PTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MBOX_POLLING_MS		5	/* polling interval 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct altera_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bool is_sender;		/* 1-sender, 0-receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	bool intr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *mbox_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct mbox_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* If the controller supports only RX polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct timer_list rxpoll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static struct altera_mbox *mbox_chan_to_altera_mbox(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (!chan || !chan->con_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return (struct altera_mbox *)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static inline int altera_mbox_full(struct altera_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return MBOX_FULL(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline int altera_mbox_pending(struct altera_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return MBOX_PENDING(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void altera_mbox_rx_intmask(struct altera_mbox *mbox, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		mask |= INT_PENDING_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		mask &= ~INT_PENDING_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void altera_mbox_tx_intmask(struct altera_mbox *mbox, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		mask |= INT_SPACE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		mask &= ~INT_SPACE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static bool altera_mbox_is_sender(struct altera_mbox *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Write a magic number to PTR register and read back this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * This register is read-write if it is a sender.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	#define MBOX_MAGIC	0xA5A5AA55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel_relaxed(MBOX_MAGIC, mbox->mbox_base + MAILBOX_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	reg = readl_relaxed(mbox->mbox_base + MAILBOX_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (reg == MBOX_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		/* Clear to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		writel_relaxed(0, mbox->mbox_base + MAILBOX_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void altera_mbox_rx_data(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (altera_mbox_pending(mbox)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		data[MBOX_PTR] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			readl_relaxed(mbox->mbox_base + MAILBOX_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		data[MBOX_CMD] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			readl_relaxed(mbox->mbox_base + MAILBOX_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		mbox_chan_received_data(chan, (void *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void altera_mbox_poll_rx(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct altera_mbox *mbox = from_timer(mbox, t, rxpoll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	altera_mbox_rx_data(mbox->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mod_timer(&mbox->rxpoll_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		  jiffies + msecs_to_jiffies(MBOX_POLLING_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static irqreturn_t altera_mbox_tx_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct mbox_chan *chan = (struct mbox_chan *)p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	altera_mbox_tx_intmask(mbox, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mbox_chan_txdone(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t altera_mbox_rx_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct mbox_chan *chan = (struct mbox_chan *)p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	altera_mbox_rx_data(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int altera_mbox_startup_sender(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (mbox->intr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ret = request_irq(mbox->irq, altera_mbox_tx_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				  DRIVER_NAME, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			dev_err(mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				"failed to register mailbox interrupt:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int altera_mbox_startup_receiver(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (mbox->intr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = request_irq(mbox->irq, altera_mbox_rx_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				  DRIVER_NAME, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			mbox->intr_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			goto polling; /* use polling if failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		altera_mbox_rx_intmask(mbox, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) polling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Setup polling timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mbox->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	timer_setup(&mbox->rxpoll_timer, altera_mbox_poll_rx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mod_timer(&mbox->rxpoll_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		  jiffies + msecs_to_jiffies(MBOX_POLLING_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int altera_mbox_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 *udata = (u32 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!mbox || !data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!mbox->is_sender) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_warn(mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			 "failed to send. This is receiver mailbox.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (altera_mbox_full(mbox))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Enable interrupt before send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (mbox->intr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		altera_mbox_tx_intmask(mbox, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Pointer register must write before command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	writel_relaxed(udata[MBOX_PTR], mbox->mbox_base + MAILBOX_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	writel_relaxed(udata[MBOX_CMD], mbox->mbox_base + MAILBOX_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static bool altera_mbox_last_tx_done(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Return false if mailbox is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return altera_mbox_full(mbox) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static bool altera_mbox_peek_data(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return altera_mbox_pending(mbox) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int altera_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (!mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (mbox->is_sender)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ret = altera_mbox_startup_sender(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ret = altera_mbox_startup_receiver(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void altera_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct altera_mbox *mbox = mbox_chan_to_altera_mbox(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (mbox->intr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		/* Unmask all interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		writel_relaxed(~0, mbox->mbox_base + MAILBOX_INTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		free_irq(mbox->irq, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	} else if (!mbox->is_sender) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		del_timer_sync(&mbox->rxpoll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct mbox_chan_ops altera_mbox_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.send_data = altera_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.startup = altera_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.shutdown = altera_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.last_tx_done = altera_mbox_last_tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.peek_data = altera_mbox_peek_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int altera_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct altera_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct resource	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct mbox_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (!mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* Allocated one channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mbox->mbox_base = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (IS_ERR(mbox->mbox_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return PTR_ERR(mbox->mbox_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* Check is it a sender or receiver? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	mbox->is_sender = altera_mbox_is_sender(mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	mbox->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (mbox->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		mbox->intr_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	mbox->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Hardware supports only one channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	chans[0].con_priv = mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	mbox->controller.dev = mbox->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	mbox->controller.num_chans = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	mbox->controller.chans = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mbox->controller.ops = &altera_mbox_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (mbox->is_sender) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		if (mbox->intr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			mbox->controller.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			mbox->controller.txdone_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			mbox->controller.txpoll_period = MBOX_POLLING_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		dev_err(&pdev->dev, "Register mailbox failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	platform_set_drvdata(pdev, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct of_device_id altera_mbox_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{ .compatible = "altr,mailbox-1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{ /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DEVICE_TABLE(of, altera_mbox_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct platform_driver altera_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.probe	= altera_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.of_match_table	= altera_mbox_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) module_platform_driver(altera_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_DESCRIPTION("Altera mailbox specific functions");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_ALIAS("platform:altera-mailbox");