Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hisilicon's Hi6220 mailbox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2015 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Leo Yan <leo.yan@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MBOX_CHAN_MAX			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MBOX_TX				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Mailbox message length: 8 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MBOX_MSG_LEN			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Mailbox Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MBOX_OFF(m)			(0x40 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MBOX_MODE_REG(m)		(MBOX_OFF(m) + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MBOX_DATA_REG(m)		(MBOX_OFF(m) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MBOX_STATE_MASK			(0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MBOX_STATE_IDLE			(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MBOX_STATE_TX			(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MBOX_STATE_RX			(0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MBOX_STATE_ACK			(0x8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MBOX_ACK_CONFIG_MASK		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MBOX_ACK_AUTOMATIC		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MBOX_ACK_IRQ			(0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* IPC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ACK_INT_RAW_REG(i)		((i) + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ACK_INT_MSK_REG(i)		((i) + 0x404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ACK_INT_STAT_REG(i)		((i) + 0x408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ACK_INT_CLR_REG(i)		((i) + 0x40c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ACK_INT_ENA_REG(i)		((i) + 0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ACK_INT_DIS_REG(i)		((i) + 0x504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DST_INT_RAW_REG(i)		((i) + 0x420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct hi6220_mbox_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * Description for channel's hardware info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 *  - direction: tx or rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 *  - dst irq: peer core's irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 *  - ack irq: local irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 *  - slot number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int dir, dst_irq, ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct hi6220_mbox *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct hi6220_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* flag of enabling tx's irq mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	bool tx_irq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* region for ipc event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* region for mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned int chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct hi6220_mbox_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	void *irq_map_chan[MBOX_CHAN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct mbox_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void mbox_set_state(struct hi6220_mbox *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			   unsigned int slot, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	status = readl(mbox->base + MBOX_MODE_REG(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	status = (status & ~MBOX_STATE_MASK) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	writel(status, mbox->base + MBOX_MODE_REG(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static void mbox_set_mode(struct hi6220_mbox *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			  unsigned int slot, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mode = readl(mbox->base + MBOX_MODE_REG(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mode = (mode & ~MBOX_ACK_CONFIG_MASK) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writel(mode, mbox->base + MBOX_MODE_REG(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static bool hi6220_mbox_last_tx_done(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct hi6220_mbox_chan *mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct hi6220_mbox *mbox = mchan->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Only set idle state for polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	BUG_ON(mbox->tx_irq_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	state = readl(mbox->base + MBOX_MODE_REG(mchan->slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return ((state & MBOX_STATE_MASK) == MBOX_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int hi6220_mbox_send_data(struct mbox_chan *chan, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct hi6220_mbox_chan *mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct hi6220_mbox *mbox = mchan->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int slot = mchan->slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 *buf = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* indicate as a TX channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	mchan->dir = MBOX_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mbox_set_state(mbox, slot, MBOX_STATE_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (mbox->tx_irq_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		mbox_set_mode(mbox, slot, MBOX_ACK_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		mbox_set_mode(mbox, slot, MBOX_ACK_AUTOMATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	for (i = 0; i < MBOX_MSG_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* trigger remote request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static irqreturn_t hi6220_mbox_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct hi6220_mbox *mbox = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct hi6220_mbox_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned int state, intr_bit, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 msg[MBOX_MSG_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	state = readl(ACK_INT_STAT_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_warn(mbox->dev, "%s: spurious interrupt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			 __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	while (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		intr_bit = __ffs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		state &= (state - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		chan = mbox->irq_map_chan[intr_bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			dev_warn(mbox->dev, "%s: unexpected irq vector %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				 __func__, intr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (mchan->dir == MBOX_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			mbox_chan_txdone(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			for (i = 0; i < MBOX_MSG_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				msg[i] = readl(mbox->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					MBOX_DATA_REG(mchan->slot) + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			mbox_chan_received_data(chan, (void *)msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* clear IRQ source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		mbox_set_state(mbox, mchan->slot, MBOX_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int hi6220_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct hi6220_mbox_chan *mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct hi6220_mbox *mbox = mchan->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mchan->dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void hi6220_mbox_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct hi6220_mbox_chan *mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct hi6220_mbox *mbox = mchan->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mbox->irq_map_chan[mchan->ack_irq] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct mbox_chan_ops hi6220_mbox_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.send_data    = hi6220_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.startup      = hi6220_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.shutdown     = hi6220_mbox_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.last_tx_done = hi6220_mbox_last_tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct mbox_chan *hi6220_mbox_xlate(struct mbox_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					   const struct of_phandle_args *spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct hi6220_mbox *mbox = dev_get_drvdata(controller->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct hi6220_mbox_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unsigned int i = spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int dst_irq = spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	unsigned int ack_irq = spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* Bounds checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (i >= mbox->chan_num || dst_irq >= mbox->chan_num ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	    ack_irq >= mbox->chan_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_err(mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			"Invalid channel idx %d dst_irq %d ack_irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			i, dst_irq, ack_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Is requested channel free? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	chan = &mbox->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (mbox->irq_map_chan[ack_irq] == (void *)chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(mbox->dev, "Channel in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mchan = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mchan->dst_irq = dst_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	mchan->ack_irq = ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mbox->irq_map_chan[ack_irq] = (void *)chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct of_device_id hi6220_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ .compatible = "hisilicon,hi6220-mbox", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DEVICE_TABLE(of, hi6220_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int hi6220_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct hi6220_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (!mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	mbox->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mbox->chan_num = MBOX_CHAN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	mbox->mchan = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		mbox->chan_num, sizeof(*mbox->mchan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!mbox->mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mbox->chan = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		mbox->chan_num, sizeof(*mbox->chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!mbox->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	mbox->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (mbox->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return mbox->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mbox->ipc = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (IS_ERR(mbox->ipc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dev_err(dev, "ioremap ipc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return PTR_ERR(mbox->ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mbox->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (IS_ERR(mbox->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_err(dev, "ioremap buffer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return PTR_ERR(mbox->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	err = devm_request_irq(dev, mbox->irq, hi6220_mbox_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			dev_name(dev), mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mbox->controller.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	mbox->controller.chans = &mbox->chan[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mbox->controller.num_chans = mbox->chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	mbox->controller.ops = &hi6220_mbox_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mbox->controller.of_xlate = hi6220_mbox_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	for (i = 0; i < mbox->chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		mbox->chan[i].con_priv = &mbox->mchan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		mbox->irq_map_chan[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		mbox->mchan[i].parent = mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		mbox->mchan[i].slot   = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* mask and clear all interrupt vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	writel(0x0,  ACK_INT_MSK_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	writel(~0x0, ACK_INT_CLR_REG(mbox->ipc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* use interrupt for tx's ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (of_find_property(node, "hi6220,mbox-tx-noirq", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		mbox->tx_irq_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		mbox->tx_irq_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (mbox->tx_irq_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		mbox->controller.txdone_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		mbox->controller.txdone_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		mbox->controller.txpoll_period = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	err = devm_mbox_controller_register(dev, &mbox->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(dev, "Failed to register mailbox %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	platform_set_drvdata(pdev, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	dev_info(dev, "Mailbox enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct platform_driver hi6220_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.name = "hi6220-mbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.of_match_table = hi6220_mbox_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.probe	= hi6220_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int __init hi6220_mbox_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return platform_driver_register(&hi6220_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) core_initcall(hi6220_mbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void __exit hi6220_mbox_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	platform_driver_unregister(&hi6220_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) module_exit(hi6220_mbox_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DESCRIPTION("Hi6220 mailbox driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_LICENSE("GPL v2");