^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-2018 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2017-2018 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "mailbox.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MBOX_CHAN_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MBOX_RX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MBOX_TX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MBOX_SRC_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MBOX_DST_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MBOX_DCLR_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MBOX_DSTAT_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MBOX_MODE_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MBOX_IMASK_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MBOX_ICLR_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MBOX_SEND_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MBOX_DATA_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MBOX_IPC_LOCK_REG 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MBOX_IPC_UNLOCK 0x1acce551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MBOX_AUTOMATIC_ACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MBOX_STATE_IDLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MBOX_STATE_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MBOX_STATE_ACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MBOX_MSG_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Hi3660 mailbox channel information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * A channel can be used for TX or RX, it can trigger remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * processor interrupt to notify remote processor and can receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * interrupt if has incoming message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @dst_irq: Interrupt vector for remote processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @ack_irq: Interrupt vector for local processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct hi3660_chan_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int dst_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Hi3660 mailbox controller data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Mailbox controller includes 32 channels and can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * channel for message transferring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @dev: Device to which it is attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @base: Base address of the register mapping region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @chan: Representation of channels in mailbox controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @mchan: Representation of channel info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @controller: Representation of a communication channel controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct hi3660_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mbox_chan chan[MBOX_CHAN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct hi3660_chan_info mchan[MBOX_CHAN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mbox_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return container_of(mbox, struct hi3660_mbox, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int hi3660_mbox_check_state(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long ch = (unsigned long)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct hi3660_chan_info *mchan = &mbox->mchan[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *base = MBOX_BASE(mbox, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Mailbox is ready to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (readl(base + MBOX_MODE_REG) & MBOX_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Wait for acknowledge from remote */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = readx_poll_timeout_atomic(readl, base + MBOX_MODE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val, (val & MBOX_STATE_ACK), 1000, 300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* clear ack state, mailbox will get back to ready state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int hi3660_mbox_unlock(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int val, retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = readl(mbox->base + MBOX_IPC_LOCK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } while (retry--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(mbox->dev, "%s: failed to unlock mailbox\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return (!val) ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int hi3660_mbox_acquire_channel(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long ch = (unsigned long)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct hi3660_chan_info *mchan = &mbox->mchan[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *base = MBOX_BASE(mbox, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int val, retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) for (retry = 10; retry; retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Check if channel is in idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Check ack bit has been set successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = readl(base + MBOX_SRC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (val & BIT(mchan->ack_irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(mbox->dev, "%s: failed to acquire channel\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return retry ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int hi3660_mbox_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = hi3660_mbox_unlock(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = hi3660_mbox_acquire_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long ch = (unsigned long)chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct hi3660_chan_info *mchan = &mbox->mchan[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __iomem *base = MBOX_BASE(mbox, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 *buf = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = hi3660_mbox_check_state(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Clear mask for destination interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Config destination for interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Automatic acknowledge mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Fill message data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (i = 0; i < MBOX_MSG_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Trigger data transferring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct mbox_chan_ops hi3660_mbox_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .startup = hi3660_mbox_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .send_data = hi3660_mbox_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct of_phandle_args *spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct hi3660_mbox *mbox = to_hi3660_mbox(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct hi3660_chan_info *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int ch = spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ch >= MBOX_CHAN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(mbox->dev, "Invalid channel idx %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mchan = &mbox->mchan[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mchan->dst_irq = spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mchan->ack_irq = spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return &mbox->chan[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id hi3660_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .compatible = "hisilicon,hi3660-mbox", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int hi3660_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct hi3660_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mbox->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (IS_ERR(mbox->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PTR_ERR(mbox->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mbox->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mbox->controller.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mbox->controller.chans = mbox->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mbox->controller.num_chans = MBOX_CHAN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mbox->controller.ops = &hi3660_mbox_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mbox->controller.of_xlate = hi3660_mbox_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Initialize mailbox channel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) chan = mbox->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (ch = 0; ch < MBOX_CHAN_MAX; ch++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) chan[ch].con_priv = (void *)ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = devm_mbox_controller_register(dev, &mbox->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(dev, "Failed to register mailbox %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) platform_set_drvdata(pdev, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_info(dev, "Mailbox enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct platform_driver hi3660_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .probe = hi3660_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "hi3660-mbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .of_match_table = hi3660_mbox_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int __init hi3660_mbox_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return platform_driver_register(&hi3660_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) core_initcall(hi3660_mbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void __exit hi3660_mbox_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) platform_driver_unregister(&hi3660_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) module_exit(hi3660_mbox_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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