^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Broadcom PDC Mailbox Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The PDC provides a ring based programming interface to one or more hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * offload engines. For example, the PDC driver works with both SPU-M and SPU2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * cryptographic offload hardware. In some chips the PDC is referred to as MDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and in others the FA2/FA+ hardware is used with this PDC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The PDC driver registers with the Linux mailbox framework as a mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * controller, once for each PDC instance. Ring 0 for each PDC is registered as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * a mailbox channel. The PDC driver uses interrupts to determine when data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * transfers to and from an offload engine are complete. The PDC driver uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * threaded IRQs so that response messages are handled outside of interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * The PDC driver allows multiple messages to be pending in the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * rings. The tx_msg_start descriptor index indicates where the last message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * starts. The txin_numd value at this index indicates how many descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * indexes make up the message. Similar state is kept on the receive side. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * an rx interrupt indicates a response is ready, the PDC driver processes numd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * descriptors from the tx and rx ring, thus processing one response at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/mailbox/brcm-message.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PDC_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RING_ENTRY_SIZE sizeof(struct dma64dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* # entries in PDC dma ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PDC_RING_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Minimum number of ring descriptor entries that must be free to tell mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * framework that it can submit another request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDC_RING_SPACE_MIN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDC_RING_SIZE (PDC_RING_ENTRIES * RING_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Rings are 8k aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RING_ALIGN_ORDER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RING_ALIGN BIT(RING_ALIGN_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RX_BUF_ALIGN_ORDER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RX_BUF_ALIGN BIT(RX_BUF_ALIGN_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* descriptor bumping macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XXD(x, max_mask) ((x) & (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TXD(x, max_mask) XXD((x), (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RXD(x, max_mask) XXD((x), (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NEXTTXD(i, max_mask) TXD((i) + 1, (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NEXTRXD(i, max_mask) RXD((i) + 1, (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Length of BCM header at start of SPU msg, in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BCM_HDR_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * PDC driver reserves ringset 0 on each SPU for its own use. The driver does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * not currently support use of multiple ringsets on a single PDC engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PDC_RINGSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Interrupt mask and status definitions. Enable interrupts for tx and rx on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * ring 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PDC_RCVINT_0 (16 + PDC_RINGSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PDC_INTMASK (PDC_RCVINTEN_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PDC_LAZY_FRAMECOUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PDC_LAZY_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PDC_LAZY_INT (PDC_LAZY_TIMEOUT | (PDC_LAZY_FRAMECOUNT << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PDC_INTMASK_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PDC_INTSTATUS_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FA_RCVLAZY0_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * before frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PDC_SPU2_RESP_HDR_LEN 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PDC_CKSUM_CTRL BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PDC_CKSUM_CTRL_OFFSET 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PDC_SPUM_RESP_HDR_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Sets the following bits for write to transmit control reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 11 - PtyChkDisable - parity check is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PDC_TX_CTL 0x000C0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Bit in tx control reg to enable tx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PDC_TX_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Sets the following bits for write to receive control reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 9 - SepRxHdrDescEn - place start of new frames only in descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * that have StartOfFrame set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * remaining bytes in current frame, report error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * in rx frame status for current frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 11 - PtyChkDisable - parity check is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PDC_RX_CTL 0x000C0E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Bit in rx control reg to enable rx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PDC_RX_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* descriptor flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define D64_CTRL1_EOT BIT(28) /* end of descriptor table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define D64_CTRL1_IOC BIT(29) /* interrupt on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define D64_CTRL1_EOF BIT(30) /* end of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define D64_CTRL1_SOF BIT(31) /* start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RX_STATUS_OVERFLOW 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RX_STATUS_LEN 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PDC_TXREGS_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PDC_RXREGS_OFFSET 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Maximum size buffer the DMA engine can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PDC_DMA_BUF_MAX 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum pdc_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FA_HW, /* FA2/FA+ hardware (i.e. Northstar Plus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pdc_dma_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void *ctx; /* opaque context associated with frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* dma descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct dma64dd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 ctrl1; /* misc control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 ctrl2; /* buffer count and address extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 addrlow; /* memory address of the date buffer, bits 31:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* dma registers per channel(xmt or rcv) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dma64_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 control; /* enable, et al */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 ptr; /* last descriptor posted to chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 addrlow; /* descriptor ring base address low 32-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 addrhigh; /* descriptor ring base address bits 63:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 status0; /* last rx descriptor written by hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 status1; /* driver does not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* cpp contortions to concatenate w/arg prescan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifndef PAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define _PADLINE(line) pad ## line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define _XSTR(line) _PADLINE(line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PAD _XSTR(__LINE__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif /* PAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* dma registers. matches hw layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dma64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct dma64_regs dmaxmt; /* dma tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 PAD[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct dma64_regs dmarcv; /* dma rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 PAD[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* PDC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pdc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 devcontrol; /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 devstatus; /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 biststatus; /* 0x00c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 PAD[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 intstatus; /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 intmask; /* 0x024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 gptimer; /* 0x028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 intrcvlazy_0; /* 0x030 (Only in PDC, not FA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 intrcvlazy_1; /* 0x034 (Only in PDC, not FA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 intrcvlazy_2; /* 0x038 (Only in PDC, not FA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 intrcvlazy_3; /* 0x03c (Only in PDC, not FA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 PAD[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 fa_intrecvlazy; /* 0x100 (Only in FA2, not PDC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 flowctlthresh; /* 0x104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 wrrthresh; /* 0x108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 gmac_idle_cnt_thresh; /* 0x10c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 PAD[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 ifioaccessaddr; /* 0x120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 ifioaccessbyte; /* 0x124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 ifioaccessdata; /* 0x128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 PAD[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 phyaccess; /* 0x180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 phycontrol; /* 0x188 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 txqctl; /* 0x18c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 rxqctl; /* 0x190 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 gpioselect; /* 0x194 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 gpio_output_en; /* 0x198 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 PAD; /* 0x19c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 txq_rxq_mem_ctl; /* 0x1a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 memory_ecc_status; /* 0x1a4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 serdes_ctl; /* 0x1a8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 serdes_status0; /* 0x1ac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 serdes_status1; /* 0x1b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 PAD[11]; /* 0x1b4-1dc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 clk_ctl_st; /* 0x1e0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 hw_war; /* 0x1e4 (Only in PDC, not FA2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 pwrctl; /* 0x1e8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 PAD[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PDC_NUM_DMA_RINGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* more registers follow, but we don't use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* structure for allocating/freeing DMA rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct pdc_ring_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dma_addr_t dmabase; /* DMA address of start of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void *vbase; /* base kernel virtual address of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 size; /* ring allocation size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * context associated with a receive descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @rxp_ctx: opaque context associated with frame that starts at each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * rx ring index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @dst_sg: Scatterlist used to form reply frames beginning at a given ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * index. Retained in order to unmap each sg after reply is processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @rxin_numd: Number of rx descriptors associated with the message that starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * at a descriptor index. Not set for every index. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * if descriptor index i points to a scatterlist with 4 entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * then the next three descriptor indexes don't have a value set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @resp_hdr: Virtual address of buffer used to catch DMA rx status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @resp_hdr_daddr: physical address of DMA rx status buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct pdc_rx_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void *rxp_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct scatterlist *dst_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 rxin_numd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void *resp_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dma_addr_t resp_hdr_daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* PDC state structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct pdc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Index of the PDC whose state is in this structure instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 pdc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Platform device for this PDC instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Each PDC instance has a mailbox controller. PDC receives request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * messages through mailboxes, and sends response messages through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * mailbox framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct mbox_controller mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int pdc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* tasklet for deferred processing after DMA rx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tasklet_struct rx_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Number of bytes of receive status prior to each rx frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 rx_status_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Whether a BCM header is prepended to each frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool use_bcm_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Sum of length of BCM header and rx status header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 pdc_resp_hdr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* The base virtual address of DMA hw registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *pdc_reg_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Pool for allocation of DMA rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dma_pool *ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Pool for allocation of metadata buffers for response messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct dma_pool *rx_buf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * The base virtual address of DMA tx/rx descriptor rings. Corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * DMA address and size of ring allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pdc_ring_alloc tx_ring_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pdc_ring_alloc rx_ring_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pdc_regs *regs; /* start of PDC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct dma64_regs *txregs_64; /* dma tx engine registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct dma64_regs *rxregs_64; /* dma rx engine registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Arrays of PDC_RING_ENTRIES descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * To use multiple ringsets, this needs to be extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct dma64dd *txd_64; /* tx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct dma64dd *rxd_64; /* rx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* descriptor ring sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 ntxd; /* # tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 nrxd; /* # rx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 nrxpost; /* # rx buffers to keep posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 ntxpost; /* max number of tx buffers that can be posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Index of next tx descriptor to reclaim. That is, the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * index of the oldest tx buffer for which the host has yet to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * the corresponding response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 txin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Index of the first receive descriptor for the sequence of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * message fragments currently under construction. Used to build up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * the rxin_numd count for a message. Updated to rxout when the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * starts a new sequence of rx buffers for a new message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 tx_msg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Index of next tx descriptor to post. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 txout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Number of tx descriptors associated with the message that starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * at this tx descriptor index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 txin_numd[PDC_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Index of next rx descriptor to reclaim. This is the index of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * the next descriptor whose data has yet to be processed by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 rxin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Index of the first receive descriptor for the sequence of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * message fragments currently under construction. Used to build up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * the rxin_numd count for a message. Updated to rxout when the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * starts a new sequence of rx buffers for a new message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 rx_msg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Saved value of current hardware rx descriptor index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * The last rx buffer written by the hw is the index previous to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * this one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 last_rx_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Index of next rx descriptor to post. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 rxout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct pdc_rx_ctx rx_ctx[PDC_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Scatterlists used to form request and reply frames beginning at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * given ring index. Retained in order to unmap each sg after reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * is processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct scatterlist *src_sg[PDC_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 pdc_requests; /* number of request messages submitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 pdc_replies; /* number of reply messages received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 last_tx_not_done; /* too few tx descriptors to indicate done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 tx_ring_full; /* unable to accept msg because tx ring full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 rx_ring_full; /* unable to accept msg because rx ring full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 txnobuf; /* unable to create tx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 rxnobuf; /* unable to create rx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 rx_oflow; /* count of rx overflows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* hardware type - FA2 or PDC/MDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) enum pdc_hw hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Global variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct pdc_globals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Actual number of SPUs in hardware, as reported by device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 num_spu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct pdc_globals pdcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* top level debug FS directory for PDC driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) size_t count, loff_t *offp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct pdc_state *pdcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ssize_t ret, out_offset, out_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) out_count = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) buf = kmalloc(out_count, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pdcs = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) out_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "SPU %u stats:\n", pdcs->pdc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "PDC requests....................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pdcs->pdc_requests);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "PDC responses...................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pdcs->pdc_replies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "Tx not done.....................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pdcs->last_tx_not_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Tx ring full....................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pdcs->tx_ring_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "Rx ring full....................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pdcs->rx_ring_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "Tx desc write fail. Ring full...%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pdcs->txnobuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "Rx desc write fail. Ring full...%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pdcs->rxnobuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "Receive overflow................%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pdcs->rx_oflow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) out_offset += scnprintf(buf + out_offset, out_count - out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Num frags in rx ring............%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pdcs->nrxpost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (out_offset > out_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) out_offset = out_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct file_operations pdc_debugfs_stats = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .read = pdc_debugfs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * directory has not yet been created, create it now. Create a stats file in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * this directory for a SPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * @pdcs: PDC state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void pdc_setup_debugfs(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) char spu_stats_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!debugfs_initialized())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!debugfs_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* S_IRUSR == 0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) debugfs_create_file(spu_stats_name, 0400, debugfs_dir, pdcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &pdc_debugfs_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void pdc_free_debugfs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) debugfs_remove_recursive(debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) debugfs_dir = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * @pdcs: PDC state for SPU that will generate result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * @dma_addr: DMA address of buffer that descriptor is being built for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @buf_len: Length of the receive buffer, in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @flags: Flags to be stored in descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 buf_len, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pdcs->pdc_idx, pdcs->rxout, buf_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) rxd->ctrl1 = cpu_to_le32(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) rxd->ctrl2 = cpu_to_le32(buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* bump ring index and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @pdcs: PDC state for the SPU that will process this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @dma_addr: DMA address of packet to be transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * @buf_len: Length of tx buffer, in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * @flags: Flags to be stored in descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct dma64dd *txd = &pdcs->txd_64[pdcs->txout];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pdcs->pdc_idx, pdcs->txout, buf_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) txd->ctrl1 = cpu_to_le32(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) txd->ctrl2 = cpu_to_le32(buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* bump ring index and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * pdc_receive_one() - Receive a response message from a given SPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * @pdcs: PDC state for the SPU to receive from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * When the return code indicates success, the response message is available in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * the receive buffers provided prior to submission of the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Return: PDC_SUCCESS if one or more receive descriptors was processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * -EAGAIN indicates that no response message is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * -EIO an error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pdc_receive_one(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct mbox_controller *mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct brcm_message mssg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 len, rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 num_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 *resp_hdr; /* virtual addr of start of resp message DMA header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 frags_rdy; /* number of fragments ready to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 rx_idx; /* ring index of start of receive frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma_addr_t resp_hdr_daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct pdc_rx_ctx *rx_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mbc = &pdcs->mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) chan = &mbc->chans[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mssg.type = BRCM_MESSAGE_SPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * return if a complete response message is not yet ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * rxin_numd[rxin] is the number of fragments in the next msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if ((frags_rdy == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* No response ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) num_frags = pdcs->txin_numd[pdcs->txin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) WARN_ON(num_frags == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(dev, "PDC %u reclaimed %d tx descriptors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pdcs->pdc_idx, num_frags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rx_idx = pdcs->rxin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rx_ctx = &pdcs->rx_ctx[rx_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) num_frags = rx_ctx->rxin_numd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Return opaque context with result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mssg.ctx = rx_ctx->rxp_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rx_ctx->rxp_ctx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) resp_hdr = rx_ctx->resp_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) resp_hdr_daddr = rx_ctx->resp_hdr_daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(dev, "PDC %u reclaimed %d rx descriptors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pdcs->pdc_idx, num_frags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pdcs->rxout, pdcs->last_rx_curr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * For SPU-M, get length of response msg and rx overflow status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rx_status = *((u32 *)resp_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) len = rx_status & RX_STATUS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "SPU response length %u bytes", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (unlikely(((rx_status & RX_STATUS_OVERFLOW) || (!len)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (rx_status & RX_STATUS_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "crypto receive overflow");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pdcs->rx_oflow++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_info_ratelimited(dev, "crypto rx len = 0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mbox_chan_received_data(chan, &mssg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pdcs->pdc_replies++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * pdc_receive() - Process as many responses as are available in the rx ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @pdcs: PDC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Called within the hard IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pdc_receive(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* read last_rx_curr from register once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pdcs->last_rx_curr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) (ioread32((const void __iomem *)&pdcs->rxregs_64->status0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Could be many frames ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rx_status = pdc_receive_one(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } while (rx_status == PDC_SUCCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * descriptors for a given SPU. The scatterlist buffers contain the data for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * SPU request message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @spu_idx: The index of the SPU to submit the request to, [0, max_spu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @sg: Scatterlist whose buffers contain part of the SPU request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * If a scatterlist buffer is larger than PDC_DMA_BUF_MAX, multiple descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * are written for that buffer, each <= PDC_DMA_BUF_MAX byte in length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Return: PDC_SUCCESS if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * < 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 eot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 tx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Num descriptors needed. Conservatively assume we need a descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * for every entry in sg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 num_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 desc_w = 0; /* Number of tx descriptors written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dma_addr_t databufptr; /* DMA address to put in descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) num_desc = (u32)sg_nents(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* check whether enough tx descriptors are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pdcs->ntxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (unlikely(num_desc > tx_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pdcs->txnobuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* build tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (pdcs->tx_msg_start == pdcs->txout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pdcs->txin_numd[pdcs->tx_msg_start] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pdcs->src_sg[pdcs->txout] = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) flags = D64_CTRL1_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) while (sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) eot = D64_CTRL1_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) eot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * If sg buffer larger than PDC limit, split across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * multiple descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) bufcnt = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) databufptr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) while (bufcnt > PDC_DMA_BUF_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pdc_build_txd(pdcs, databufptr, PDC_DMA_BUF_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) flags | eot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) desc_w++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bufcnt -= PDC_DMA_BUF_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) databufptr += PDC_DMA_BUF_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) eot = D64_CTRL1_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) eot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Writing last descriptor for frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) flags |= (D64_CTRL1_EOF | D64_CTRL1_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pdc_build_txd(pdcs, databufptr, bufcnt, flags | eot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) desc_w++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Clear start of frame after first descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) flags &= ~D64_CTRL1_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) pdcs->txin_numd[pdcs->tx_msg_start] += desc_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * @pdcs: PDC state for SPU to process the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * Sets the index of the last descriptor written in both the rx and tx ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Return: PDC_SUCCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int pdc_tx_list_final(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * write barrier to ensure all register writes are complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * before chip starts to process new request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pdcs->pdc_requests++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * @pdcs: PDC state for SPU handling request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * @dst_sg: scatterlist providing rx buffers for response to be returned to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * mailbox client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * @ctx: Opaque context for this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Posts a single receive descriptor to hold the metadata that precedes a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * rx to indicate the start of a new message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * Return: PDC_SUCCESS if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * < 0 if an error (e.g., rx ring is full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 rx_pkt_cnt = 1; /* Adding a single rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dma_addr_t daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct pdc_rx_ctx *rx_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pdcs->nrxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (unlikely(rx_pkt_cnt > rx_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pdcs->rxnobuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* allocate a buffer for the dma rx status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (unlikely(!vaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * Update msg_start indexes for both tx and rx to indicate the start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * of a new sequence of descriptor indexes that contain the fragments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * of the same message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pdcs->rx_msg_start = pdcs->rxout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pdcs->tx_msg_start = pdcs->txout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* This is always the first descriptor in the receive sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) flags = D64_CTRL1_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) flags |= D64_CTRL1_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) rx_ctx = &pdcs->rx_ctx[pdcs->rxout];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rx_ctx->rxp_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rx_ctx->dst_sg = dst_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rx_ctx->resp_hdr = vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) rx_ctx->resp_hdr_daddr = daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * descriptors for a given SPU. The caller must have already DMA mapped the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * scatterlist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * @spu_idx: Indicates which SPU the buffers are for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @sg: Scatterlist whose buffers are added to the receive ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * If a receive buffer in the scatterlist is larger than PDC_DMA_BUF_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * multiple receive descriptors are written, each with a buffer <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * PDC_DMA_BUF_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Return: PDC_SUCCESS if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * < 0 otherwise (e.g., receive ring is full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * Num descriptors needed. Conservatively assume we need a descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * for every entry from our starting point in the scatterlist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 num_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 desc_w = 0; /* Number of tx descriptors written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dma_addr_t databufptr; /* DMA address to put in descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) num_desc = (u32)sg_nents(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pdcs->nrxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (unlikely(num_desc > rx_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pdcs->rxnobuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) while (sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) flags = D64_CTRL1_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * If sg buffer larger than PDC limit, split across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * multiple descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) bufcnt = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) databufptr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) while (bufcnt > PDC_DMA_BUF_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pdc_build_rxd(pdcs, databufptr, PDC_DMA_BUF_MAX, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) desc_w++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bufcnt -= PDC_DMA_BUF_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) databufptr += PDC_DMA_BUF_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) flags = D64_CTRL1_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pdc_build_rxd(pdcs, databufptr, bufcnt, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) desc_w++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * pdc_irq_handler() - Interrupt handler called in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * @irq: Interrupt number that has fired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * @data: device struct for DMA engine that generated the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * We have to clear the device interrupt status flags here. So cache the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * status for later use in the thread function. Other than that, just return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * WAKE_THREAD to invoke the thread function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * Return: IRQ_WAKE_THREAD if interrupt is ours
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * IRQ_NONE otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static irqreturn_t pdc_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct device *dev = (struct device *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct pdc_state *pdcs = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (unlikely(intstatus == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Disable interrupts until soft handler runs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Clear interrupt flags in device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Wakeup IRQ thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) tasklet_schedule(&pdcs->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * pdc_tasklet_cb() - Tasklet callback that runs the deferred processing after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * a DMA receive interrupt. Reenables the receive interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * @data: PDC state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static void pdc_tasklet_cb(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct pdc_state *pdcs = from_tasklet(pdcs, t, rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) pdc_receive(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* reenable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * descriptors in one ringset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @pdcs: PDC instance state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * @ringset: index of ringset being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * Return: PDC_SUCCESS if ring initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * < 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int err = PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct dma64 *dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct pdc_ring_alloc tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct pdc_ring_alloc rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Allocate tx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (unlikely(!tx.vbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Allocate rx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (unlikely(!rx.vbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) goto fail_dealloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pdcs->rxin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pdcs->rx_msg_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pdcs->last_rx_curr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pdcs->rxout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pdcs->txin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) pdcs->tx_msg_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pdcs->txout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Set descriptor array base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Tell device the base DMA address of each ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dma_reg = &pdcs->regs->dmaregs[ringset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* But first disable DMA and set curptr to 0 for both TX & RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &dma_reg->dmarcv.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) iowrite32(0, &dma_reg->dmaxmt.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) iowrite32(0, &dma_reg->dmarcv.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Set base DMA addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &dma_reg->dmaxmt.addrlow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) &dma_reg->dmaxmt.addrhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) &dma_reg->dmarcv.addrlow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &dma_reg->dmarcv.addrhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Re-enable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) &dma_reg->dmarcv.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Initialize descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (i = 0; i < PDC_RING_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Every tx descriptor can be used for start of frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (i != pdcs->ntxpost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) &pdcs->txd_64[i].ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Last descriptor in ringset. Set End of Table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Every rx descriptor can be used for start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (i != pdcs->nrxpost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) iowrite32(D64_CTRL1_SOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) &pdcs->rxd_64[i].ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Last descriptor in ringset. Set End of Table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) &pdcs->rxd_64[i].ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) fail_dealloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void pdc_ring_free(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (pdcs->tx_ring_alloc.vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pdcs->tx_ring_alloc.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pdcs->tx_ring_alloc.vbase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (pdcs->rx_ring_alloc.vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pdcs->rx_ring_alloc.dmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pdcs->rx_ring_alloc.vbase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * pdc_desc_count() - Count the number of DMA descriptors that will be required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * for a given scatterlist. Account for the max length of a DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * @sg: Scatterlist to be DMA'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * Return: Number of descriptors required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static u32 pdc_desc_count(struct scatterlist *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u32 cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) while (sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * and the rx ring has room for rx_cnt descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * @pdcs: PDC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * @tx_cnt: The number of descriptors required in the tx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * @rx_cnt: The number of descriptors required i the rx ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Return: true if one of the rings does not have enough space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * false if sufficient space is available in both rings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u32 rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 tx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) bool full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Check if the tx and rx rings are likely to have enough space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pdcs->nrxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (unlikely(rx_cnt > rx_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pdcs->rx_ring_full++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) full = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (likely(!full)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pdcs->ntxpost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (unlikely(tx_cnt > tx_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pdcs->tx_ring_full++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) full = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * pdc_last_tx_done() - If both the tx and rx rings have at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * framework can submit another message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * @chan: mailbox channel to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * Return: true if PDC can accept another message on this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static bool pdc_last_tx_done(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct pdc_state *pdcs = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (unlikely(pdc_rings_full(pdcs, PDC_RING_SPACE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PDC_RING_SPACE_MIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pdcs->last_tx_not_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * pdc_send_data() - mailbox send_data function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * @chan: The mailbox channel on which the data is sent. The channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * corresponds to a DMA ringset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * @data: The mailbox message to be sent. The message must be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * brcm_message structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * This function is registered as the send_data function for the mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * controller. From the destination scatterlist in the mailbox message, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * creates a sequence of receive descriptors in the rx ring. From the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * scatterlist, it creates a sequence of transmit descriptors in the tx ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * After creating the descriptors, it writes the rx ptr and tx ptr registers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * initiate the DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * This function does the DMA map and unmap of the src and dst scatterlists in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * the mailbox message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * Return: 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * -ENOTSUPP if the mailbox message is a type this driver does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * < 0 if an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int pdc_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct pdc_state *pdcs = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct brcm_message *mssg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int err = PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) int src_nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int dst_nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int nent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) u32 tx_desc_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) u32 rx_desc_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (unlikely(mssg->type != BRCM_MESSAGE_SPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) src_nent = sg_nents(mssg->spu.src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (likely(src_nent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (unlikely(nent == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dst_nent = sg_nents(mssg->spu.dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (likely(dst_nent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) nent = dma_map_sg(dev, mssg->spu.dst, dst_nent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (unlikely(nent == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dma_unmap_sg(dev, mssg->spu.src, src_nent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * Check if the tx and rx rings have enough space. Do this prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * writing any tx or rx descriptors. Need to ensure that we do not write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * a partial set of descriptors, or write just rx descriptors but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * corresponding tx descriptors don't fit. Note that we want this check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * and the entire sequence of descriptor to happen without another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * thread getting in. The channel spin lock in the mailbox framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * ensures this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) tx_desc_req = pdc_desc_count(mssg->spu.src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rx_desc_req = pdc_desc_count(mssg->spu.dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (unlikely(pdc_rings_full(pdcs, tx_desc_req, rx_desc_req + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Create rx descriptors to SPU catch response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Create tx descriptors to submit SPU request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) err |= pdc_tx_list_final(pdcs); /* initiate transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_err(&pdcs->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "%s failed with error %d", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int pdc_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return pdc_ring_init(chan->con_priv, PDC_RINGSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void pdc_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct pdc_state *pdcs = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dev_dbg(&pdcs->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pdc_ring_free(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * pdc_hw_init() - Use the given initialization parameters to initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * state for one of the PDCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * @pdcs: state of the PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) void pdc_hw_init(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct dma64 *dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int ringset = PDC_RINGSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pdev = pdcs->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_dbg(dev, "state structure: %p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_dbg(dev, " - base virtual addr of hw regs %p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pdcs->pdc_reg_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* initialize data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pdcs->txregs_64 = (struct dma64_regs *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) (((u8 *)pdcs->pdc_reg_vbase) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pdcs->rxregs_64 = (struct dma64_regs *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (((u8 *)pdcs->pdc_reg_vbase) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pdcs->ntxd = PDC_RING_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) pdcs->nrxd = PDC_RING_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) pdcs->ntxpost = PDC_RING_ENTRIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) pdcs->nrxpost = PDC_RING_ENTRIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) iowrite32(0, &pdcs->regs->intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dma_reg = &pdcs->regs->dmaregs[ringset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Configure DMA but will enable later in pdc_ring_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) &dma_reg->dmarcv.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* Reset current index pointers after making sure DMA is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) iowrite32(0, &dma_reg->dmaxmt.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) iowrite32(0, &dma_reg->dmarcv.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) iowrite32(PDC_CKSUM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * pdc_hw_disable() - Disable the tx and rx control in the hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * @pdcs: PDC state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static void pdc_hw_disable(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct dma64 *dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) &dma_reg->dmarcv.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * header returned with each response message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * @pdcs: PDC state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * The metadata is not returned to the mailbox client. So the PDC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * manages these buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * Return: PDC_SUCCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * -ENOMEM if pool creation fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int pdc_rx_buf_pool_create(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pdev = pdcs->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pdcs->pdc_resp_hdr_len = pdcs->rx_status_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (pdcs->use_bcm_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pdcs->pdc_resp_hdr_len += BCM_HDR_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pdcs->pdc_resp_hdr_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) RX_BUF_ALIGN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!pdcs->rx_buf_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * specify a threaded IRQ handler for deferred handling of interrupts outside of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * @pdcs: PDC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * Set the interrupt mask for transmit and receive done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * Set the lazy interrupt frame count to generate an interrupt for just one pkt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * Return: PDC_SUCCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * <0 if threaded irq request fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static int pdc_interrupts_init(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct platform_device *pdev = pdcs->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* interrupt configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (pdcs->hw_type == FA_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) FA_RCVLAZY0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PDC_RCVLAZY0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* read irq from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_dbg(dev, "pdc device %s irq %u for pdcs %p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_name(dev), pdcs->pdc_irq, pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_name(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev_err(dev, "IRQ %u request failed with err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pdcs->pdc_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const struct mbox_chan_ops pdc_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .send_data = pdc_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .last_tx_done = pdc_last_tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .startup = pdc_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .shutdown = pdc_shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * pdc_mb_init() - Initialize the mailbox controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * @pdcs: PDC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * driver only uses one ringset and thus one mb channel. PDC uses the transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * complete interrupt to determine when a mailbox message has successfully been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * < 0 if there is an allocation or registration failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int pdc_mb_init(struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct device *dev = &pdcs->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct mbox_controller *mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int chan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) mbc = &pdcs->mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) mbc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mbc->ops = &pdc_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) mbc->num_chans = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!mbc->chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) mbc->txdone_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) mbc->txdone_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) mbc->txpoll_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) for (chan_index = 0; chan_index < mbc->num_chans; chan_index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mbc->chans[chan_index].con_priv = pdcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Register mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) err = devm_mbox_controller_register(dev, mbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev_crit(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) "Failed to register PDC mailbox controller. Error %d.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* Device tree API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static const int pdc_hw = PDC_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const int fa_hw = FA_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const struct of_device_id pdc_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * pdc_dt_read() - Read application-specific data from device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * @pdev: Platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * @pdcs: PDC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * Reads the number of bytes of receive status that precede each received frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * Reads whether transmit and received frames should be preceded by an 8-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * BCM header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * Return: 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * -ENODEV if device not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) const int *hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) err = of_property_read_u32(dn, "brcm,rx-status-len",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) &pdcs->rx_status_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) "%s failed to get DMA receive status length from device tree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pdcs->hw_type = PDC_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) match = of_match_device(of_match_ptr(pdc_mbox_of_match), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (match != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) hw_type = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pdcs->hw_type = *hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * pdc_probe() - Probe function for PDC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * @pdev: PDC platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * Reserve and map register regions defined in device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * Allocate and initialize tx and rx DMA rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * Initialize a mailbox controller for each PDC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * Return: 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * < 0 if an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static int pdc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct resource *pdc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct pdc_state *pdcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* PDC state for one SPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pdcs = devm_kzalloc(dev, sizeof(*pdcs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!pdcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) pdcs->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) platform_set_drvdata(pdev, pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pdcs->pdc_idx = pdcg.num_spu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) pdcg.num_spu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(39));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* Create DMA pool for tx ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) RING_ALIGN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (!pdcs->ring_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) err = pdc_dt_read(pdev, pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) goto cleanup_ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pdc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (!pdc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto cleanup_ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) &pdc_regs->start, &pdc_regs->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (IS_ERR(pdcs->pdc_reg_vbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err = PTR_ERR(pdcs->pdc_reg_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_err(&pdev->dev, "Failed to map registers: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) goto cleanup_ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* create rx buffer pool after dt read to know how big buffers are */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) err = pdc_rx_buf_pool_create(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) goto cleanup_ring_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pdc_hw_init(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* Init tasklet for deferred DMA rx processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) tasklet_setup(&pdcs->rx_tasklet, pdc_tasklet_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) err = pdc_interrupts_init(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) goto cleanup_buf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* Initialize mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) err = pdc_mb_init(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) goto cleanup_buf_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) pdc_setup_debugfs(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_dbg(dev, "pdc_probe() successful");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return PDC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) cleanup_buf_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) tasklet_kill(&pdcs->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dma_pool_destroy(pdcs->rx_buf_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) cleanup_ring_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dma_pool_destroy(pdcs->ring_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static int pdc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct pdc_state *pdcs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pdc_free_debugfs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) tasklet_kill(&pdcs->rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) pdc_hw_disable(pdcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dma_pool_destroy(pdcs->rx_buf_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dma_pool_destroy(pdcs->ring_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static struct platform_driver pdc_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .probe = pdc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .remove = pdc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .name = "brcm-iproc-pdc-mbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .of_match_table = of_match_ptr(pdc_mbox_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) module_platform_driver(pdc_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MODULE_AUTHOR("Rob Rice <rob.rice@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MODULE_DESCRIPTION("Broadcom PDC mailbox driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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