^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Broadcom FlexRM Mailbox Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Each Broadcom FlexSparx4 offload engine is implemented as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * extension to Broadcom FlexRM ring manager. The FlexRM ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * manager provides a set of rings which can be used to submit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * work to a FlexSparx4 offload engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This driver creates a mailbox controller using a set of FlexRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * rings where each mailbox channel represents a separate FlexRM ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/mailbox/brcm-message.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ====== FlexRM register defines ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* FlexRM configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RING_REGS_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RING_DESC_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RING_DESC_INDEX(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ((offset) / RING_DESC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RING_DESC_OFFSET(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ((index) * RING_DESC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RING_MAX_REQ_COUNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RING_BD_ALIGN_ORDER 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RING_BD_ALIGN_CHECK(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (!((addr) & ((0x1 << RING_BD_ALIGN_ORDER) - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RING_BD_TOGGLE_INVALID(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (((offset) >> RING_BD_ALIGN_ORDER) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RING_BD_TOGGLE_VALID(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (!RING_BD_TOGGLE_INVALID(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RING_BD_DESC_PER_REQ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RING_BD_DESC_COUNT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (RING_MAX_REQ_COUNT * RING_BD_DESC_PER_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RING_BD_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (RING_BD_DESC_COUNT * RING_DESC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RING_CMPL_ALIGN_ORDER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RING_CMPL_DESC_COUNT RING_MAX_REQ_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RING_CMPL_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (RING_CMPL_DESC_COUNT * RING_DESC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RING_VER_MAGIC 0x76303031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Per-Ring register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RING_VER 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RING_BD_START_ADDR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RING_BD_READ_PTR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RING_BD_WRITE_PTR 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RING_BD_READ_PTR_DDR_LS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RING_BD_READ_PTR_DDR_MS 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RING_CMPL_START_ADDR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RING_CMPL_WRITE_PTR 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RING_NUM_REQ_RECV_LS 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RING_NUM_REQ_RECV_MS 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RING_NUM_REQ_TRANS_LS 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RING_NUM_REQ_TRANS_MS 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RING_NUM_REQ_OUTSTAND 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RING_CONTROL 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RING_FLUSH_DONE 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RING_MSI_ADDR_LS 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RING_MSI_ADDR_MS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RING_MSI_CONTROL 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RING_BD_READ_PTR_DDR_CONTROL 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RING_MSI_DATA_VALUE 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Register RING_BD_START_ADDR fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BD_LAST_UPDATE_HW_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BD_LAST_UPDATE_HW_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BD_START_ADDR_VALUE(pa) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ((u32)((((dma_addr_t)(pa)) >> RING_BD_ALIGN_ORDER) & 0x0fffffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BD_START_ADDR_DECODE(val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ((dma_addr_t)((val) & 0x0fffffff) << RING_BD_ALIGN_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Register RING_CMPL_START_ADDR fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMPL_START_ADDR_VALUE(pa) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x07ffffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Register RING_CONTROL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CONTROL_MASK_DISABLE_CONTROL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CONTROL_FLUSH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CONTROL_ACTIVE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CONTROL_RATE_ADAPT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CONTROL_RATE_DYNAMIC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CONTROL_RATE_FAST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CONTROL_RATE_MEDIUM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CONTROL_RATE_SLOW 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CONTROL_RATE_IDLE 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Register RING_FLUSH_DONE fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FLUSH_DONE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Register RING_MSI_CONTROL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSI_TIMER_VAL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MSI_TIMER_VAL_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MSI_ENABLE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSI_ENABLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MSI_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSI_COUNT_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Register RING_BD_READ_PTR_DDR_CONTROL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BD_READ_PTR_DDR_TIMER_VAL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BD_READ_PTR_DDR_TIMER_VAL_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BD_READ_PTR_DDR_ENABLE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BD_READ_PTR_DDR_ENABLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* ====== FlexRM ring descriptor defines ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Completion descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMPL_OPAQUE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMPL_OPAQUE_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMPL_ENGINE_STATUS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMPL_ENGINE_STATUS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMPL_DME_STATUS_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMPL_DME_STATUS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMPL_RM_STATUS_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMPL_RM_STATUS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Completion DME status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DME_STATUS_MEM_COR_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DME_STATUS_MEM_UCOR_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DME_STATUS_FIFO_UNDERFLOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DME_STATUS_FIFO_OVERFLOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DME_STATUS_RRESP_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DME_STATUS_BRESP_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DME_STATUS_ERROR_MASK (DME_STATUS_MEM_COR_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DME_STATUS_MEM_UCOR_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DME_STATUS_FIFO_UNDERFLOW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DME_STATUS_FIFO_OVERFLOW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DME_STATUS_RRESP_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DME_STATUS_BRESP_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Completion RM status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RM_STATUS_CODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RM_STATUS_CODE_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RM_STATUS_CODE_GOOD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RM_STATUS_CODE_AE_TIMEOUT 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* General descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DESC_TYPE_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DESC_TYPE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DESC_PAYLOAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DESC_PAYLOAD_MASK 0x0fffffffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Null descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define NULL_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NULL_TOGGLE_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define NULL_TOGGLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Header descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HEADER_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HEADER_TOGGLE_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HEADER_TOGGLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HEADER_ENDPKT_SHIFT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HEADER_ENDPKT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HEADER_STARTPKT_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HEADER_STARTPKT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HEADER_BDCOUNT_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HEADER_BDCOUNT_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HEADER_BDCOUNT_MAX HEADER_BDCOUNT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HEADER_FLAGS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HEADER_FLAGS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HEADER_OPAQUE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HEADER_OPAQUE_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Source (SRC) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SRC_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SRC_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRC_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRC_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SRC_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Destination (DST) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DST_TYPE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DST_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DST_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DST_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DST_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Immediate (IMM) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMM_TYPE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMM_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMM_DATA_MASK 0x0fffffffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Next pointer (NPTR) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define NPTR_TYPE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define NPTR_TOGGLE_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define NPTR_TOGGLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NPTR_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NPTR_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Mega source (MSRC) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MSRC_TYPE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MSRC_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MSRC_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MSRC_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MSRC_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Mega destination (MDST) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MDST_TYPE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MDST_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MDST_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MDST_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MDST_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Source with tlast (SRCT) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRCT_TYPE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRCT_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRCT_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRCT_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRCT_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Destination with tlast (DSTT) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DSTT_TYPE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DSTT_LENGTH_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DSTT_LENGTH_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DSTT_ADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DSTT_ADDR_MASK 0x00000fffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Immediate with tlast (IMMT) descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMMT_TYPE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMMT_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMMT_DATA_MASK 0x0fffffffffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Descriptor helper macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DESC_DEC(_d, _s, _m) (((_d) >> (_s)) & (_m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DESC_ENC(_d, _v, _s, _m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (_d) &= ~((u64)(_m) << (_s)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (_d) |= (((u64)(_v) & (_m)) << (_s)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ====== FlexRM data structures ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct flexrm_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Unprotected members */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct flexrm_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bool irq_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cpumask_t irq_aff_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int msi_timer_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int msi_count_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct brcm_message *requests[RING_MAX_REQ_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void *bd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_addr_t bd_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 bd_write_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void *cmpl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dma_addr_t cmpl_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Atomic stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) atomic_t msg_send_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) atomic_t msg_cmpl_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Protected members */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_BITMAP(requests_bmap, RING_MAX_REQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 cmpl_read_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct flexrm_mbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 num_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct flexrm_ring *rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct dma_pool *bd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct dma_pool *cmpl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct mbox_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* ====== FlexRM ring descriptor helper routines ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static u64 flexrm_read_desc(void *desc_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return le64_to_cpu(*((u64 *)desc_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void flexrm_write_desc(void *desc_ptr, u64 desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *((u64 *)desc_ptr) = cpu_to_le64(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static u32 flexrm_cmpl_desc_to_reqid(u64 cmpl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return (u32)(cmpl_desc & CMPL_OPAQUE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int flexrm_cmpl_desc_to_error(u64 cmpl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) status = DESC_DEC(cmpl_desc, CMPL_DME_STATUS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CMPL_DME_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (status & DME_STATUS_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) status = DESC_DEC(cmpl_desc, CMPL_RM_STATUS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CMPL_RM_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) status &= RM_STATUS_CODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (status == RM_STATUS_CODE_AE_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static bool flexrm_is_next_table_desc(void *desc_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u64 desc = flexrm_read_desc(desc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 type = DESC_DEC(desc, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return (type == NPTR_TYPE) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static u64 flexrm_next_table_desc(u32 toggle, dma_addr_t next_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DESC_ENC(desc, NPTR_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DESC_ENC(desc, toggle, NPTR_TOGGLE_SHIFT, NPTR_TOGGLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DESC_ENC(desc, next_addr, NPTR_ADDR_SHIFT, NPTR_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static u64 flexrm_null_desc(u32 toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DESC_ENC(desc, NULL_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DESC_ENC(desc, toggle, NULL_TOGGLE_SHIFT, NULL_TOGGLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static u32 flexrm_estimate_header_desc_count(u32 nhcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 hcnt = nhcnt / HEADER_BDCOUNT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!(nhcnt % HEADER_BDCOUNT_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hcnt += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void flexrm_flip_header_toggle(void *desc_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u64 desc = flexrm_read_desc(desc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (desc & ((u64)0x1 << HEADER_TOGGLE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) desc &= ~((u64)0x1 << HEADER_TOGGLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) desc |= ((u64)0x1 << HEADER_TOGGLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) flexrm_write_desc(desc_ptr, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static u64 flexrm_header_desc(u32 toggle, u32 startpkt, u32 endpkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 bdcount, u32 flags, u32 opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DESC_ENC(desc, HEADER_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DESC_ENC(desc, toggle, HEADER_TOGGLE_SHIFT, HEADER_TOGGLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DESC_ENC(desc, startpkt, HEADER_STARTPKT_SHIFT, HEADER_STARTPKT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DESC_ENC(desc, endpkt, HEADER_ENDPKT_SHIFT, HEADER_ENDPKT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DESC_ENC(desc, bdcount, HEADER_BDCOUNT_SHIFT, HEADER_BDCOUNT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DESC_ENC(desc, flags, HEADER_FLAGS_SHIFT, HEADER_FLAGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DESC_ENC(desc, opaque, HEADER_OPAQUE_SHIFT, HEADER_OPAQUE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void flexrm_enqueue_desc(u32 nhpos, u32 nhcnt, u32 reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u64 desc, void **desc_ptr, u32 *toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) void *start_desc, void *end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 nhavail, _toggle, _startpkt, _endpkt, _bdcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (nhcnt <= nhpos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Each request or packet start with a HEADER descriptor followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * by one or more non-HEADER descriptors (SRC, SRCT, MSRC, DST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * DSTT, MDST, IMM, and IMMT). The number of non-HEADER descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * following a HEADER descriptor is represented by BDCOUNT field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * of HEADER descriptor. The max value of BDCOUNT field is 31 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * means we can only have 31 non-HEADER descriptors following one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * HEADER descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * In general use, number of non-HEADER descriptors can easily go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * beyond 31. To tackle this situation, we have packet (or request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * extenstion bits (STARTPKT and ENDPKT) in the HEADER descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * To use packet extension, the first HEADER descriptor of request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * (or packet) will have STARTPKT=1 and ENDPKT=0. The intermediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * HEADER descriptors will have STARTPKT=0 and ENDPKT=0. The last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * HEADER descriptor will have STARTPKT=0 and ENDPKT=1. Also, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * TOGGLE bit of the first HEADER will be set to invalid state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * ensure that FlexRM does not start fetching descriptors till all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * descriptors are enqueued. The user of this function will flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * the TOGGLE bit of first HEADER after all descriptors are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * enqueued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if ((nhpos % HEADER_BDCOUNT_MAX == 0) && (nhcnt - nhpos)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Prepare the header descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) nhavail = (nhcnt - nhpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) _toggle = (nhpos == 0) ? !(*toggle) : (*toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) _startpkt = (nhpos == 0) ? 0x1 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) _endpkt = (nhavail <= HEADER_BDCOUNT_MAX) ? 0x1 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) _bdcount = (nhavail <= HEADER_BDCOUNT_MAX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) nhavail : HEADER_BDCOUNT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (nhavail <= HEADER_BDCOUNT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) _bdcount = nhavail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) _bdcount = HEADER_BDCOUNT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) d = flexrm_header_desc(_toggle, _startpkt, _endpkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) _bdcount, 0x0, reqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Write header descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) flexrm_write_desc(*desc_ptr, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Point to next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *desc_ptr += sizeof(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (*desc_ptr == end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *desc_ptr = start_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Skip next pointer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) while (flexrm_is_next_table_desc(*desc_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *toggle = (*toggle) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *desc_ptr += sizeof(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (*desc_ptr == end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *desc_ptr = start_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Write desired descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) flexrm_write_desc(*desc_ptr, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Point to next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *desc_ptr += sizeof(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (*desc_ptr == end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *desc_ptr = start_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Skip next pointer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) while (flexrm_is_next_table_desc(*desc_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *toggle = (*toggle) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *desc_ptr += sizeof(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (*desc_ptr == end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *desc_ptr = start_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static u64 flexrm_src_desc(dma_addr_t addr, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DESC_ENC(desc, SRC_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DESC_ENC(desc, length, SRC_LENGTH_SHIFT, SRC_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DESC_ENC(desc, addr, SRC_ADDR_SHIFT, SRC_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static u64 flexrm_msrc_desc(dma_addr_t addr, unsigned int length_div_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DESC_ENC(desc, MSRC_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DESC_ENC(desc, length_div_16, MSRC_LENGTH_SHIFT, MSRC_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DESC_ENC(desc, addr, MSRC_ADDR_SHIFT, MSRC_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static u64 flexrm_dst_desc(dma_addr_t addr, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DESC_ENC(desc, DST_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DESC_ENC(desc, length, DST_LENGTH_SHIFT, DST_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DESC_ENC(desc, addr, DST_ADDR_SHIFT, DST_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static u64 flexrm_mdst_desc(dma_addr_t addr, unsigned int length_div_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DESC_ENC(desc, MDST_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DESC_ENC(desc, length_div_16, MDST_LENGTH_SHIFT, MDST_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) DESC_ENC(desc, addr, MDST_ADDR_SHIFT, MDST_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static u64 flexrm_imm_desc(u64 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DESC_ENC(desc, IMM_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DESC_ENC(desc, data, IMM_DATA_SHIFT, IMM_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static u64 flexrm_srct_desc(dma_addr_t addr, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DESC_ENC(desc, SRCT_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DESC_ENC(desc, length, SRCT_LENGTH_SHIFT, SRCT_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DESC_ENC(desc, addr, SRCT_ADDR_SHIFT, SRCT_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static u64 flexrm_dstt_desc(dma_addr_t addr, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DESC_ENC(desc, DSTT_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) DESC_ENC(desc, length, DSTT_LENGTH_SHIFT, DSTT_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) DESC_ENC(desc, addr, DSTT_ADDR_SHIFT, DSTT_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static u64 flexrm_immt_desc(u64 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u64 desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DESC_ENC(desc, IMMT_TYPE, DESC_TYPE_SHIFT, DESC_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DESC_ENC(desc, data, IMMT_DATA_SHIFT, IMMT_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static bool flexrm_spu_sanity_check(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!msg->spu.src || !msg->spu.dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (sg = msg->spu.src; sg; sg = sg_next(sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (sg->length & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (sg->length > SRC_LENGTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (sg->length > (MSRC_LENGTH_MASK * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (sg = msg->spu.dst; sg; sg = sg_next(sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (sg->length & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (sg->length > DST_LENGTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (sg->length > (MDST_LENGTH_MASK * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static u32 flexrm_spu_estimate_nonheader_desc_count(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int dst_target = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct scatterlist *src_sg = msg->spu.src, *dst_sg = msg->spu.dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) while (src_sg || dst_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (src_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dst_target = src_sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) src_sg = sg_next(src_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dst_target = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) while (dst_target && dst_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (dst_sg->length < dst_target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dst_target -= dst_sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dst_target = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dst_sg = sg_next(dst_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int flexrm_spu_dma_map(struct device *dev, struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) rc = dma_map_sg(dev, msg->spu.src, sg_nents(msg->spu.src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rc = dma_map_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void flexrm_spu_dma_unmap(struct device *dev, struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dma_unmap_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void *flexrm_spu_write_descs(struct brcm_message *msg, u32 nhcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 reqid, void *desc_ptr, u32 toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void *start_desc, void *end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 nhpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void *orig_desc_ptr = desc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned int dst_target = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct scatterlist *src_sg = msg->spu.src, *dst_sg = msg->spu.dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) while (src_sg || dst_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (src_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (sg_dma_len(src_sg) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) d = flexrm_src_desc(sg_dma_address(src_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sg_dma_len(src_sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) d = flexrm_msrc_desc(sg_dma_address(src_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sg_dma_len(src_sg)/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dst_target = sg_dma_len(src_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) src_sg = sg_next(src_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dst_target = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) while (dst_target && dst_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (sg_dma_len(dst_sg) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) d = flexrm_dst_desc(sg_dma_address(dst_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) sg_dma_len(dst_sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) d = flexrm_mdst_desc(sg_dma_address(dst_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sg_dma_len(dst_sg)/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (sg_dma_len(dst_sg) < dst_target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dst_target -= sg_dma_len(dst_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dst_target = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dst_sg = sg_next(dst_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Null descriptor with invalid toggle bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) flexrm_write_desc(desc_ptr, flexrm_null_desc(!toggle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Ensure that descriptors have been written to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Flip toggle bit in header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) flexrm_flip_header_toggle(orig_desc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return desc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static bool flexrm_sba_sanity_check(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!msg->sba.cmds || !msg->sba.cmds_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (i = 0; i < msg->sba.cmds_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (((msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_B) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_C)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) (msg->sba.cmds[i].flags & BRCM_SBA_CMD_HAS_OUTPUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if ((msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_B) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (msg->sba.cmds[i].data_len > SRCT_LENGTH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if ((msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_C) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) (msg->sba.cmds[i].data_len > SRCT_LENGTH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if ((msg->sba.cmds[i].flags & BRCM_SBA_CMD_HAS_RESP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) (msg->sba.cmds[i].resp_len > DSTT_LENGTH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if ((msg->sba.cmds[i].flags & BRCM_SBA_CMD_HAS_OUTPUT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (msg->sba.cmds[i].data_len > DSTT_LENGTH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static u32 flexrm_sba_estimate_nonheader_desc_count(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 i, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) for (i = 0; i < msg->sba.cmds_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if ((msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_B) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (msg->sba.cmds[i].flags & BRCM_SBA_CMD_TYPE_C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (msg->sba.cmds[i].flags & BRCM_SBA_CMD_HAS_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (msg->sba.cmds[i].flags & BRCM_SBA_CMD_HAS_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void *flexrm_sba_write_descs(struct brcm_message *msg, u32 nhcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 reqid, void *desc_ptr, u32 toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) void *start_desc, void *end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 i, nhpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct brcm_sba_command *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void *orig_desc_ptr = desc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Convert SBA commands into descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for (i = 0; i < msg->sba.cmds_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) c = &msg->sba.cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if ((c->flags & BRCM_SBA_CMD_HAS_RESP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) (c->flags & BRCM_SBA_CMD_HAS_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Destination response descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) d = flexrm_dst_desc(c->resp, c->resp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } else if (c->flags & BRCM_SBA_CMD_HAS_RESP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Destination response with tlast descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) d = flexrm_dstt_desc(c->resp, c->resp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (c->flags & BRCM_SBA_CMD_HAS_OUTPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Destination with tlast descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) d = flexrm_dstt_desc(c->data, c->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (c->flags & BRCM_SBA_CMD_TYPE_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Command as immediate descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) d = flexrm_imm_desc(c->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Command as immediate descriptor with tlast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) d = flexrm_immt_desc(c->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((c->flags & BRCM_SBA_CMD_TYPE_B) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (c->flags & BRCM_SBA_CMD_TYPE_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Source with tlast descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) d = flexrm_srct_desc(c->data, c->data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) flexrm_enqueue_desc(nhpos, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) d, &desc_ptr, &toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) nhpos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Null descriptor with invalid toggle bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) flexrm_write_desc(desc_ptr, flexrm_null_desc(!toggle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Ensure that descriptors have been written to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Flip toggle bit in header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) flexrm_flip_header_toggle(orig_desc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return desc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static bool flexrm_sanity_check(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) switch (msg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case BRCM_MESSAGE_SPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return flexrm_spu_sanity_check(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case BRCM_MESSAGE_SBA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return flexrm_sba_sanity_check(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static u32 flexrm_estimate_nonheader_desc_count(struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) switch (msg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case BRCM_MESSAGE_SPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return flexrm_spu_estimate_nonheader_desc_count(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case BRCM_MESSAGE_SBA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return flexrm_sba_estimate_nonheader_desc_count(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int flexrm_dma_map(struct device *dev, struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!dev || !msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) switch (msg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case BRCM_MESSAGE_SPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return flexrm_spu_dma_map(dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static void flexrm_dma_unmap(struct device *dev, struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!dev || !msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (msg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case BRCM_MESSAGE_SPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) flexrm_spu_dma_unmap(dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void *flexrm_write_descs(struct brcm_message *msg, u32 nhcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 reqid, void *desc_ptr, u32 toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) void *start_desc, void *end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!msg || !desc_ptr || !start_desc || !end_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if ((desc_ptr < start_desc) || (end_desc <= desc_ptr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ERR_PTR(-ERANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) switch (msg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case BRCM_MESSAGE_SPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return flexrm_spu_write_descs(msg, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) desc_ptr, toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case BRCM_MESSAGE_SBA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return flexrm_sba_write_descs(msg, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) desc_ptr, toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) start_desc, end_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* ====== FlexRM driver helper routines ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void flexrm_write_config_in_seqfile(struct flexrm_mbox *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct seq_file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) const char *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct flexrm_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) seq_printf(file, "%-5s %-9s %-18s %-10s %-18s %-10s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "Ring#", "State", "BD_Addr", "BD_Size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "Cmpl_Addr", "Cmpl_Size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) for (i = 0; i < mbox->num_rings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ring = &mbox->rings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (readl(ring->regs + RING_CONTROL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) BIT(CONTROL_ACTIVE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) state = "active";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) state = "inactive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) seq_printf(file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "%-5d %-9s 0x%016llx 0x%08x 0x%016llx 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ring->num, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (unsigned long long)ring->bd_dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) (u32)RING_BD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) (unsigned long long)ring->cmpl_dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (u32)RING_CMPL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static void flexrm_write_stats_in_seqfile(struct flexrm_mbox *mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct seq_file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 val, bd_read_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct flexrm_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) seq_printf(file, "%-5s %-10s %-10s %-10s %-11s %-11s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "Ring#", "BD_Read", "BD_Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "Cmpl_Read", "Submitted", "Completed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) for (i = 0; i < mbox->num_rings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ring = &mbox->rings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) bd_read_offset = readl_relaxed(ring->regs + RING_BD_READ_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) val = readl_relaxed(ring->regs + RING_BD_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) bd_read_offset *= RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) bd_read_offset += (u32)(BD_START_ADDR_DECODE(val) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) seq_printf(file, "%-5d 0x%08x 0x%08x 0x%08x %-11d %-11d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ring->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (u32)bd_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) (u32)ring->bd_write_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) (u32)ring->cmpl_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) (u32)atomic_read(&ring->msg_send_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (u32)atomic_read(&ring->msg_cmpl_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int flexrm_new_request(struct flexrm_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct brcm_message *batch_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct brcm_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) void *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 val, count, nhcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 read_offset, write_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) bool exit_cleanup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int ret = 0, reqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Do sanity check on message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!flexrm_sanity_check(msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) msg->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* If no requests possible then save data pointer and goto done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) spin_lock_irqsave(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) reqid = bitmap_find_free_region(ring->requests_bmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RING_MAX_REQ_COUNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) spin_unlock_irqrestore(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (reqid < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ring->requests[reqid] = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Do DMA mappings for the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = flexrm_dma_map(ring->mbox->dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ring->requests[reqid] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) spin_lock_irqsave(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) bitmap_release_region(ring->requests_bmap, reqid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) spin_unlock_irqrestore(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* Determine current HW BD read offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) read_offset = readl_relaxed(ring->regs + RING_BD_READ_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) val = readl_relaxed(ring->regs + RING_BD_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) read_offset *= RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) read_offset += (u32)(BD_START_ADDR_DECODE(val) - ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Number required descriptors = number of non-header descriptors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * number of header descriptors +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * 1x null descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) nhcnt = flexrm_estimate_nonheader_desc_count(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) count = flexrm_estimate_header_desc_count(nhcnt) + nhcnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Check for available descriptor space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) write_offset = ring->bd_write_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (!flexrm_is_next_table_desc(ring->bd_base + write_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) write_offset += RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (write_offset == RING_BD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) write_offset = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (write_offset == read_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) exit_cleanup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Write descriptors to ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) next = flexrm_write_descs(msg, nhcnt, reqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ring->bd_base + ring->bd_write_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) RING_BD_TOGGLE_VALID(ring->bd_write_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ring->bd_base, ring->bd_base + RING_BD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (IS_ERR(next)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = PTR_ERR(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) exit_cleanup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Save ring BD write offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ring->bd_write_offset = (unsigned long)(next - ring->bd_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Increment number of messages sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) atomic_inc_return(&ring->msg_send_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Update error status in message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) msg->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Cleanup if we failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (exit_cleanup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) flexrm_dma_unmap(ring->mbox->dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ring->requests[reqid] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) spin_lock_irqsave(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) bitmap_release_region(ring->requests_bmap, reqid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) spin_unlock_irqrestore(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int flexrm_process_completions(struct flexrm_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u64 desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int err, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct brcm_message *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 reqid, cmpl_read_offset, cmpl_write_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct mbox_chan *chan = &ring->mbox->controller.chans[ring->num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spin_lock_irqsave(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * Get current completion read and write offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * Note: We should read completion write pointer atleast once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * after we get a MSI interrupt because HW maintains internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * MSI status which will allow next MSI interrupt only after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * completion write pointer is read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) cmpl_write_offset = readl_relaxed(ring->regs + RING_CMPL_WRITE_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) cmpl_write_offset *= RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) cmpl_read_offset = ring->cmpl_read_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ring->cmpl_read_offset = cmpl_write_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_unlock_irqrestore(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* For each completed request notify mailbox clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) reqid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) while (cmpl_read_offset != cmpl_write_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Dequeue next completion descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) desc = *((u64 *)(ring->cmpl_base + cmpl_read_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Next read offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) cmpl_read_offset += RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (cmpl_read_offset == RING_CMPL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) cmpl_read_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Decode error from completion descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) err = flexrm_cmpl_desc_to_error(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_warn(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "ring%d got completion desc=0x%lx with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ring->num, (unsigned long)desc, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Determine request id from completion descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) reqid = flexrm_cmpl_desc_to_reqid(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Determine message pointer based on reqid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) msg = ring->requests[reqid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_warn(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "ring%d null msg pointer for completion desc=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ring->num, (unsigned long)desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Release reqid for recycling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ring->requests[reqid] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) spin_lock_irqsave(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) bitmap_release_region(ring->requests_bmap, reqid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) spin_unlock_irqrestore(&ring->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Unmap DMA mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) flexrm_dma_unmap(ring->mbox->dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Give-back message to mailbox client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) msg->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) mbox_chan_received_data(chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* Increment number of completions processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) atomic_inc_return(&ring->msg_cmpl_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* ====== FlexRM Debugfs callbacks ====== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Write config in file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) flexrm_write_config_in_seqfile(mbox, file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct flexrm_mbox *mbox = dev_get_drvdata(file->private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Write stats in file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) flexrm_write_stats_in_seqfile(mbox, file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* ====== FlexRM interrupt handler ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static irqreturn_t flexrm_irq_event(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* We only have MSI for completions so just wakeup IRQ thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Ring related errors will be informed via completion descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static irqreturn_t flexrm_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) flexrm_process_completions(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* ====== FlexRM mailbox callbacks ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int flexrm_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct flexrm_ring *ring = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct brcm_message *msg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (msg->type == BRCM_MESSAGE_BATCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) for (i = msg->batch.msgs_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) i < msg->batch.msgs_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rc = flexrm_new_request(ring, msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) &msg->batch.msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) msg->error = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) msg->batch.msgs_queued++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return flexrm_new_request(ring, NULL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static bool flexrm_peek_data(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) int cnt = flexrm_process_completions(chan->con_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return (cnt > 0) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int flexrm_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) u32 val, off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dma_addr_t next_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct flexrm_ring *ring = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Allocate BD memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ring->bd_base = dma_pool_alloc(ring->mbox->bd_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) GFP_KERNEL, &ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!ring->bd_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "can't allocate BD memory for ring%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Configure next table pointer entries in BD memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) for (off = 0; off < RING_BD_SIZE; off += RING_DESC_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) next_addr = off + RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (next_addr == RING_BD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) next_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) next_addr += ring->bd_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (RING_BD_ALIGN_CHECK(next_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) d = flexrm_next_table_desc(RING_BD_TOGGLE_VALID(off),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) next_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) d = flexrm_null_desc(RING_BD_TOGGLE_INVALID(off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) flexrm_write_desc(ring->bd_base + off, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Allocate completion memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ring->cmpl_base = dma_pool_zalloc(ring->mbox->cmpl_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GFP_KERNEL, &ring->cmpl_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (!ring->cmpl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) "can't allocate completion memory for ring%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) goto fail_free_bd_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* Request IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ring->irq == UINT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "ring%d IRQ not available\n", ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) goto fail_free_cmpl_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = request_threaded_irq(ring->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) flexrm_irq_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) flexrm_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) 0, dev_name(ring->mbox->dev), ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "failed to request ring%d IRQ\n", ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto fail_free_cmpl_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ring->irq_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Set IRQ affinity hint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ring->irq_aff_hint = CPU_MASK_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val = ring->mbox->num_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) val = (num_online_cpus() < val) ? val / num_online_cpus() : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) cpumask_set_cpu((ring->num / val) % num_online_cpus(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &ring->irq_aff_hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = irq_set_affinity_hint(ring->irq, &ring->irq_aff_hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "failed to set IRQ affinity hint for ring%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) goto fail_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Disable/inactivate ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) writel_relaxed(0x0, ring->regs + RING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Program BD start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) val = BD_START_ADDR_VALUE(ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) writel_relaxed(val, ring->regs + RING_BD_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* BD write pointer will be same as HW write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ring->bd_write_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) readl_relaxed(ring->regs + RING_BD_WRITE_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ring->bd_write_offset *= RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Program completion start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) val = CMPL_START_ADDR_VALUE(ring->cmpl_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) writel_relaxed(val, ring->regs + RING_CMPL_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Completion read pointer will be same as HW write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ring->cmpl_read_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) readl_relaxed(ring->regs + RING_CMPL_WRITE_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ring->cmpl_read_offset *= RING_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Read ring Tx, Rx, and Outstanding counts to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) readl_relaxed(ring->regs + RING_NUM_REQ_RECV_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) readl_relaxed(ring->regs + RING_NUM_REQ_RECV_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) readl_relaxed(ring->regs + RING_NUM_REQ_TRANS_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) readl_relaxed(ring->regs + RING_NUM_REQ_TRANS_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) readl_relaxed(ring->regs + RING_NUM_REQ_OUTSTAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Configure RING_MSI_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) val |= (ring->msi_timer_val << MSI_TIMER_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) val |= BIT(MSI_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) val |= (ring->msi_count_threshold & MSI_COUNT_MASK) << MSI_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) writel_relaxed(val, ring->regs + RING_MSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* Enable/activate ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) val = BIT(CONTROL_ACTIVE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) writel_relaxed(val, ring->regs + RING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Reset stats to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) atomic_set(&ring->msg_send_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) atomic_set(&ring->msg_cmpl_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) fail_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) free_irq(ring->irq, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ring->irq_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) fail_free_cmpl_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dma_pool_free(ring->mbox->cmpl_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ring->cmpl_base, ring->cmpl_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ring->cmpl_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) fail_free_bd_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dma_pool_free(ring->mbox->bd_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ring->bd_base, ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ring->bd_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static void flexrm_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) u32 reqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct brcm_message *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct flexrm_ring *ring = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* Disable/inactivate ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) writel_relaxed(0x0, ring->regs + RING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Set ring flush state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) timeout = 1000; /* timeout of 1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) writel_relaxed(BIT(CONTROL_FLUSH_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ring->regs + RING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (readl_relaxed(ring->regs + RING_FLUSH_DONE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) FLUSH_DONE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) "setting ring%d flush state timedout\n", ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Clear ring flush state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) timeout = 1000; /* timeout of 1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) writel_relaxed(0x0, ring->regs + RING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (!(readl_relaxed(ring->regs + RING_FLUSH_DONE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) FLUSH_DONE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_err(ring->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) "clearing ring%d flush state timedout\n", ring->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* Abort all in-flight requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (reqid = 0; reqid < RING_MAX_REQ_COUNT; reqid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) msg = ring->requests[reqid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Release reqid for recycling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ring->requests[reqid] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Unmap DMA mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) flexrm_dma_unmap(ring->mbox->dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Give-back message to mailbox client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) msg->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) mbox_chan_received_data(chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Clear requests bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) bitmap_zero(ring->requests_bmap, RING_MAX_REQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Release IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ring->irq_requested) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) irq_set_affinity_hint(ring->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) free_irq(ring->irq, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ring->irq_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Free-up completion descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (ring->cmpl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dma_pool_free(ring->mbox->cmpl_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ring->cmpl_base, ring->cmpl_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ring->cmpl_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* Free-up BD descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (ring->bd_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dma_pool_free(ring->mbox->bd_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ring->bd_base, ring->bd_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ring->bd_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static const struct mbox_chan_ops flexrm_mbox_chan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .send_data = flexrm_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .startup = flexrm_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .shutdown = flexrm_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .peek_data = flexrm_peek_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static struct mbox_chan *flexrm_mbox_of_xlate(struct mbox_controller *cntlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) const struct of_phandle_args *pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct mbox_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct flexrm_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (pa->args_count < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (pa->args[0] >= cntlr->num_chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (pa->args[1] > MSI_COUNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (pa->args[2] > MSI_TIMER_VAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) chan = &cntlr->chans[pa->args[0]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ring = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ring->msi_count_threshold = pa->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ring->msi_timer_val = pa->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* ====== FlexRM platform driver ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static void flexrm_mbox_msi_write(struct msi_desc *desc, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct device *dev = msi_desc_to_dev(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct flexrm_mbox *mbox = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct flexrm_ring *ring = &mbox->rings[desc->platform.msi_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Configure per-Ring MSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) writel_relaxed(msg->address_lo, ring->regs + RING_MSI_ADDR_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) writel_relaxed(msg->address_hi, ring->regs + RING_MSI_ADDR_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) writel_relaxed(msg->data, ring->regs + RING_MSI_DATA_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int flexrm_mbox_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) int index, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) void __iomem *regs_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct flexrm_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct flexrm_mbox *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* Allocate driver mailbox struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (!mbox) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mbox->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) platform_set_drvdata(pdev, mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Get resource for registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!iomem || (resource_size(iomem) < RING_REGS_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Map registers of all rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) mbox->regs = devm_ioremap_resource(&pdev->dev, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (IS_ERR(mbox->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = PTR_ERR(mbox->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) regs_end = mbox->regs + resource_size(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* Scan and count available rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) mbox->num_rings = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) for (regs = mbox->regs; regs < regs_end; regs += RING_REGS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (readl_relaxed(regs + RING_VER) == RING_VER_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) mbox->num_rings++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (!mbox->num_rings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* Allocate driver ring structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ring = devm_kcalloc(dev, mbox->num_rings, sizeof(*ring), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (!ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) mbox->rings = ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Initialize members of driver ring structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) regs = mbox->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) for (index = 0; index < mbox->num_rings; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ring = &mbox->rings[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ring->num = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ring->mbox = mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) while ((regs < regs_end) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) (readl_relaxed(regs + RING_VER) != RING_VER_MAGIC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) regs += RING_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (regs_end <= regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ring->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) regs += RING_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ring->irq = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ring->irq_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ring->msi_timer_val = MSI_TIMER_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ring->msi_count_threshold = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) memset(ring->requests, 0, sizeof(ring->requests));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ring->bd_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ring->bd_dma_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ring->cmpl_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ring->cmpl_dma_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) atomic_set(&ring->msg_send_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) atomic_set(&ring->msg_cmpl_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) spin_lock_init(&ring->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) bitmap_zero(ring->requests_bmap, RING_MAX_REQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ring->cmpl_read_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* FlexRM is capable of 40-bit physical addresses only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Create DMA pool for ring BD memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) mbox->bd_pool = dma_pool_create("bd", dev, RING_BD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) 1 << RING_BD_ALIGN_ORDER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (!mbox->bd_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Create DMA pool for ring completion memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mbox->cmpl_pool = dma_pool_create("cmpl", dev, RING_CMPL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) 1 << RING_CMPL_ALIGN_ORDER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (!mbox->cmpl_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) goto fail_destroy_bd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Allocate platform MSIs for each ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ret = platform_msi_domain_alloc_irqs(dev, mbox->num_rings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) flexrm_mbox_msi_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) goto fail_destroy_cmpl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* Save alloced IRQ numbers for each ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) for_each_msi_entry(desc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ring = &mbox->rings[desc->platform.msi_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ring->irq = desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Check availability of debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (!debugfs_initialized())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) goto skip_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* Create debugfs root entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) mbox->root = debugfs_create_dir(dev_name(mbox->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* Create debugfs config entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) debugfs_create_devm_seqfile(mbox->dev, "config", mbox->root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) flexrm_debugfs_conf_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* Create debugfs stats entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) debugfs_create_devm_seqfile(mbox->dev, "stats", mbox->root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) flexrm_debugfs_stats_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) skip_debugfs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* Initialize mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mbox->controller.txdone_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mbox->controller.txdone_poll = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) mbox->controller.ops = &flexrm_mbox_chan_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) mbox->controller.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) mbox->controller.num_chans = mbox->num_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) mbox->controller.of_xlate = flexrm_mbox_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) mbox->controller.chans = devm_kcalloc(dev, mbox->num_rings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) sizeof(*mbox->controller.chans), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!mbox->controller.chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) goto fail_free_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) for (index = 0; index < mbox->num_rings; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) mbox->controller.chans[index].con_priv = &mbox->rings[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Register mailbox controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ret = devm_mbox_controller_register(dev, &mbox->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) goto fail_free_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_info(dev, "registered flexrm mailbox with %d channels\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) mbox->controller.num_chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) fail_free_debugfs_root:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) debugfs_remove_recursive(mbox->root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) platform_msi_domain_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) fail_destroy_cmpl_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dma_pool_destroy(mbox->cmpl_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) fail_destroy_bd_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dma_pool_destroy(mbox->bd_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static int flexrm_mbox_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) debugfs_remove_recursive(mbox->root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) platform_msi_domain_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) dma_pool_destroy(mbox->cmpl_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) dma_pool_destroy(mbox->bd_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const struct of_device_id flexrm_mbox_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) { .compatible = "brcm,iproc-flexrm-mbox", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) MODULE_DEVICE_TABLE(of, flexrm_mbox_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static struct platform_driver flexrm_mbox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .name = "brcm-flexrm-mbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .of_match_table = flexrm_mbox_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .probe = flexrm_mbox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .remove = flexrm_mbox_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) module_platform_driver(flexrm_mbox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) MODULE_AUTHOR("Anup Patel <anup.patel@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) MODULE_DESCRIPTION("Broadcom FlexRM mailbox driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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