^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Jassi Brar <jaswinder.singh@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INTR_STAT_OFS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INTR_SET_OFS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define INTR_CLR_OFS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MHU_LP_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MHU_HP_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MHU_SEC_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TX_REG_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MHU_CHANS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mhu_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *tx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *rx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct arm_mhu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mhu_link mlink[MHU_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mbox_chan chan[MHU_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mbox_controller mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static irqreturn_t mhu_rx_interrupt(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mbox_chan *chan = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mbox_chan_received_data(chan, (void *)&val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static bool mhu_last_tx_done(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return (val == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int mhu_send_data(struct mbox_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 *arg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int mhu_startup(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = request_irq(mlink->irq, mhu_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IRQF_SHARED, "mhu_link", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(chan->mbox->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "Unable to acquire IRQ %d\n", mlink->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void mhu_shutdown(struct mbox_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mhu_link *mlink = chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) free_irq(mlink->irq, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct mbox_chan_ops mhu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .send_data = mhu_send_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .startup = mhu_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .shutdown = mhu_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .last_tx_done = mhu_last_tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct arm_mhu *mhu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct device *dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!of_device_is_compatible(dev->of_node, "arm,mhu"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Allocate memory for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!mhu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mhu->base = devm_ioremap_resource(dev, &adev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ERR(mhu->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return PTR_ERR(mhu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < MHU_CHANS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mhu->chan[i].con_priv = &mhu->mlink[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mhu->mlink[i].irq = adev->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mhu->mbox.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mhu->mbox.chans = &mhu->chan[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mhu->mbox.num_chans = MHU_CHANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mhu->mbox.ops = &mhu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mhu->mbox.txdone_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mhu->mbox.txdone_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mhu->mbox.txpoll_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) amba_set_drvdata(adev, mhu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) err = devm_mbox_controller_register(dev, &mhu->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(dev, "Failed to register mailboxes %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_info(dev, "ARM MHU Mailbox registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct amba_id mhu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .id = 0x1bb098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_DEVICE_TABLE(amba, mhu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct amba_driver arm_mhu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "mhu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .id_table = mhu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .probe = mhu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) module_amba_driver(arm_mhu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_DESCRIPTION("ARM MHU Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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