^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device driver for the via ADB on (many) Mac II-class machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the original ADB keyboard handler Copyright (c) 1997 Alan Cox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Also derived from code Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With various updates provided over the years by Michael Schmitz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Guideo Koerber and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Rewrite for Unified ADB by Joshua M. Thompson (funaho@jurai.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 1999-08-02 (jmt) - Initial rewrite for Unified ADB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 2000-03-29 Tony Mantler <tonym@mac.linux-m68k.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Big overhaul, should actually work now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 2006-12-31 Finn Thain - Another overhaul.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Suggested reading:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Inside Macintosh, ch. 5 ADB Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Guide to the Macinstosh Family Hardware, ch. 8 Apple Desktop Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Rockwell R6522 VIA datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Apple's "ADB Analyzer" bus sniffer is invaluable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ftp://ftp.apple.com/developer/Tool_Chest/Devices_-_Hardware/Apple_Desktop_Bus/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <stdarg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/adb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/macintosh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/macints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mac_via.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static volatile unsigned char *via;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* VIA registers - spaced 0x200 bytes apart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RS 0x200 /* skip between registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define B 0 /* B-side data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define A RS /* A-side data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DIRB (2*RS) /* B-side direction (1=output) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DIRA (3*RS) /* A-side direction (1=output) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SR (10*RS) /* Shift register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ACR (11*RS) /* Auxiliary control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCR (12*RS) /* Peripheral control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IFR (13*RS) /* Interrupt flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IER (14*RS) /* Interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ANH (15*RS) /* A-side data, no handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Bits in B data register: all active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTLR_IRQ 0x08 /* Controller rcv status (input) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ST_MASK 0x30 /* mask for selecting ADB state bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Bits in ACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SR_CTRL 0x1c /* Shift register control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SR_EXT 0x0c /* Shift on external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SR_OUT 0x10 /* Shift out if 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Bits in IFR and IER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IER_SET 0x80 /* set bits in IER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IER_CLR 0 /* clear bits in IER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SR_INT 0x04 /* Shift register full/empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ADB transaction states according to GMHW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ST_CMD 0x00 /* ADB state: command byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ST_EVEN 0x10 /* ADB state: even data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ST_ODD 0x20 /* ADB state: odd data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ST_IDLE 0x30 /* ADB state: idle, nothing to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* ADB command byte structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADDR_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMD_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OP_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TALK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int macii_init_via(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void macii_start(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static irqreturn_t macii_interrupt(int irq, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void macii_queue_poll(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int macii_probe(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int macii_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int macii_send_request(struct adb_request *req, int sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int macii_write(struct adb_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int macii_autopoll(int devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void macii_poll(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int macii_reset_bus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct adb_driver via_macii_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "Mac II",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .probe = macii_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .init = macii_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .send_request = macii_send_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .autopoll = macii_autopoll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .poll = macii_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reset_bus = macii_reset_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static enum macii_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } macii_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct adb_request *current_req; /* first request struct in the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct adb_request *last_req; /* last request struct in the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static unsigned char reply_buf[16]; /* storage for autopolled replies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned char *reply_ptr; /* next byte in reply_buf or req->reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static bool reading_reply; /* store reply in reply_buf else req->reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int data_index; /* index of the next byte to send from req->data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int reply_len; /* number of bytes received in reply_buf or req->reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int status; /* VIA's ADB status bits captured upon interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static bool bus_timeout; /* no data was sent by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static bool srq_asserted; /* have to poll for the device that asserted it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static u8 last_cmd; /* the most recent command byte transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u8 last_talk_cmd; /* the most recent Talk command byte transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static u8 last_poll_cmd; /* the most recent Talk R0 command byte transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static unsigned int autopoll_devs; /* bits set are device addresses to poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Check for MacII style ADB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int macii_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (macintosh_config->adb_type != MAC_ADB_II)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) via = via1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pr_info("adb: Mac II ADB Driver v1.0 for Unified ADB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Initialize the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int macii_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) err = macii_init_via();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) err = request_irq(IRQ_MAC_ADB, macii_interrupt, 0, "ADB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) macii_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) macii_state = idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int macii_init_via(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* We want CTLR_IRQ as input and ST_EVEN | ST_ODD as output lines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) via[DIRB] = (via[DIRB] | ST_EVEN | ST_ODD) & ~CTLR_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Set up state: idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) via[B] |= ST_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Shift register on input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) via[ACR] = (via[ACR] & ~SR_CTRL) | SR_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Wipe any pending data and int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Send an ADB poll (Talk Register 0 command prepended to the request queue) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void macii_queue_poll(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct adb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned char poll_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int poll_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* This only polls devices in the autopoll list, which assumes that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * unprobed devices never assert SRQ. That could happen if a device was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * plugged in after the adb bus scan. Unplugging it again will resolve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * the problem. This behaviour is similar to MacOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!autopoll_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* The device most recently polled may not be the best device to poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * right now. Some other device(s) may have signalled SRQ (the active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * device won't do that). Or the autopoll list may have been changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Try polling the next higher address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) poll_addr = (last_poll_cmd & ADDR_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if ((srq_asserted && last_cmd == last_poll_cmd) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) !(autopoll_devs & (1 << poll_addr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int higher_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) higher_devs = autopoll_devs & -(1 << (poll_addr + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) poll_addr = ffs(higher_devs ? higher_devs : autopoll_devs) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Send a Talk Register 0 command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) poll_command = ADB_READREG(poll_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* No need to repeat this Talk command. The transceiver will do that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * as long as it is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (poll_command == last_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) adb_request(&req, NULL, ADBREQ_NOSEND, 1, poll_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) req.sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) req.complete = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) req.reply_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) req.next = current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (WARN_ON(current_req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) current_req = &req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) current_req = &req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) last_req = &req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Send an ADB request; if sync, poll out the reply 'till it's done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int macii_send_request(struct adb_request *req, int sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = macii_write(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) while (!req->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) macii_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Send an ADB request (append to request queue) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int macii_write(struct adb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (req->nbytes < 2 || req->data[0] != ADB_PACKET || req->nbytes > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) req->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) req->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) req->sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) req->complete = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) req->reply_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (current_req != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) last_req->next = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) last_req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) current_req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) last_req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (macii_state == idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) macii_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Start auto-polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int macii_autopoll(int devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* bit 1 == device 1, and so on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) autopoll_devs = (unsigned int)devs & 0xFFFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!current_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) macii_queue_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (current_req && macii_state == idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) macii_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Prod the chip without interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void macii_poll(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) macii_interrupt(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Reset the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int macii_reset_bus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct adb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Command = 0, Address = ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) adb_request(&req, NULL, ADBREQ_NOSEND, 1, ADB_BUSRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) macii_send_request(&req, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Don't want any more requests during the Global Reset low time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) udelay(3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Start sending ADB packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void macii_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct adb_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) req = current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Now send it. Be careful though, that first byte of the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * is actually ADB_PACKET; the real data begins at index 1!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * And req->nbytes is the number of bytes of real data plus one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) via[ACR] |= SR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Load data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) via[SR] = req->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* set ADB state to 'command' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) via[B] = (via[B] & ~ST_MASK) | ST_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) macii_state = sending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data_index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bus_timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) srq_asserted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * The notorious ADB interrupt handler - does all of the protocol handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Relies on the ADB controller sending and receiving data, thereby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * generating shift register interrupts (SR_INT) for us. This means there has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * to be activity on the ADB bus. The chip will poll to achieve this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The VIA Port B output signalling works as follows. After the ADB transceiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * sees a transition on the PB4 and PB5 lines it will crank over the VIA shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * register which eventually raises the SR_INT interrupt. The PB4/PB5 outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * are toggled with each byte as the ADB transaction progresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Request with no reply expected (and empty transceiver buffer):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * CMD -> IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Request with expected reply packet (or with buffered autopoll packet):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * CMD -> EVEN -> ODD -> EVEN -> ... -> IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Unsolicited packet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * IDLE -> EVEN -> ODD -> EVEN -> ... -> IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static irqreturn_t macii_interrupt(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct adb_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Clear the SR IRQ flag when polling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (via[IFR] & SR_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) via[IFR] = SR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) status = via[B] & (ST_MASK | CTLR_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (macii_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case idle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) WARN_ON((status & ST_MASK) != ST_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reply_ptr = reply_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) reading_reply = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bus_timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) srq_asserted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!(status & CTLR_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* /CTLR_IRQ asserted in idle state means we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * read an autopoll reply from the transceiver buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) macii_state = reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *reply_ptr = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) reply_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* bus timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reply_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* set ADB state = even for first data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) via[B] = (via[B] & ~ST_MASK) | ST_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case sending:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) req = current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (status == (ST_CMD | CTLR_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* /CTLR_IRQ de-asserted after the command byte means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * the host can continue with the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Store command byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) last_cmd = req->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if ((last_cmd & OP_MASK) == TALK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) last_talk_cmd = last_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((last_cmd & CMD_MASK) == ADB_READREG(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) last_poll_cmd = last_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (status == ST_CMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* /CTLR_IRQ asserted after the command byte means we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * must read an autopoll reply. The first byte was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * lost because the shift register was an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) macii_state = reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) reading_reply = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reply_ptr = reply_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *reply_ptr = last_talk_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) reply_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* reset to shift in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) via[ACR] &= ~SR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else if (data_index >= req->nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) req->sent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (req->reply_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) macii_state = reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reading_reply = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reply_ptr = req->reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *reply_ptr = req->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reply_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) via[ACR] &= ~SR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else if ((req->data[1] & OP_MASK) == TALK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) macii_state = reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reading_reply = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reply_ptr = reply_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *reply_ptr = req->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) reply_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) via[ACR] &= ~SR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) req->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) current_req = req->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (req->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (*req->done)(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) macii_state = idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) req->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) current_req = req->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (req->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (*req->done)(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) via[SR] = req->data[data_index++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if ((via[B] & ST_MASK) == ST_CMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* just sent the command byte, set to EVEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) via[B] = (via[B] & ~ST_MASK) | ST_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* invert state bits, toggle ODD/EVEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) via[B] ^= ST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case reading:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) WARN_ON((status & ST_MASK) == ST_CMD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (status & ST_MASK) == ST_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!(status & CTLR_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (status == ST_EVEN && reply_len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bus_timeout = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else if (status == ST_ODD && reply_len == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) srq_asserted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) macii_state = idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (bus_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) reply_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (reading_reply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct adb_request *req = current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) req->reply_len = reply_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) req->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) current_req = req->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (req->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (*req->done)(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else if (reply_len && autopoll_devs &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reply_buf[0] == last_poll_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) adb_input(reply_buf, reply_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (reply_len < ARRAY_SIZE(reply_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) reply_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *reply_ptr = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reply_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* invert state bits, toggle ODD/EVEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) via[B] ^= ST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (macii_state == idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!current_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) macii_queue_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (current_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) macii_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (macii_state == idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) via[ACR] &= ~SR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) x = via[SR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) via[B] = (via[B] & ~ST_MASK) | ST_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags