^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SS4200-E Hardware API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright IBM Corporation, 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Dave Hansen <dave@sr71.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ICH7 LPC/GPIO PCI Config register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMBASE 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIO_BASE 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIO_CTRL 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPIO_EN 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The ICH7 GPIO register block is 64 bytes in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ICH7_GPIO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Define register offsets within the ICH7 register block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_USE_SEL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GP_IO_SEL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GP_LVL 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPO_BLINK 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPI_INV 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_USE_SEL2 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GP_IO_SEL2 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GP_LVL2 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct pci_device_id ich7_lpc_pci_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { } /* NULL entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_info("detected '%s'\n", id->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static bool nodetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param_named(nodetect, nodetect, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * struct nas_led_whitelist - List of known good models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Contains the known good models this driver is compatible with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * When adding a new model try to be as strict as possible. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * makes it possible to keep the false positives (the model is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * detected as working, but in reality it is not) as low as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct dmi_system_id nas_led_whitelist[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .callback = ss4200_led_dmi_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ident = "Intel SS4200-E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DMI_MATCH(DMI_SYS_VENDOR, "Intel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * FUJITSU SIEMENS SCALEO Home Server/SS4200-E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * BIOS V090L 12/19/2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .callback = ss4200_led_dmi_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .ident = "Fujitsu Siemens SCALEO Home Server",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DMI_MATCH(DMI_PRODUCT_NAME, "SCALEO Home Server"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Base I/O address assigned to the Power Management register block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static u32 g_pm_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Base I/O address assigned to the ICH7 GPIO register block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u32 nas_gpio_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * When we successfully register a region, we are returned a resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * We use these to identify which regions we need to release on our way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * back out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct resource *gp_gpio_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct nasgpio_led {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct led_classdev led_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * gpio_bit(s) are the ICH7 GPIO bit assignments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct nasgpio_led nasgpio_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .name = "hdd1:blue:sata", .gpio_bit = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .name = "hdd1:amber:sata", .gpio_bit = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .name = "hdd2:blue:sata", .gpio_bit = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .name = "hdd2:amber:sata", .gpio_bit = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .name = "hdd3:blue:sata", .gpio_bit = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .name = "hdd3:amber:sata", .gpio_bit = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .name = "hdd4:blue:sata", .gpio_bit = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .name = "hdd4:amber:sata", .gpio_bit = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .name = "power:blue:power", .gpio_bit = 27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .name = "power:amber:power", .gpio_bit = 28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define NAS_RECOVERY 0x00000400 /* GPIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct nasgpio_led *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return container_of(led_cdev, struct nasgpio_led, led_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct nasgpio_led *get_led_named(char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (strcmp(nasgpio_leds[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return &nasgpio_leds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * This protects access to the gpio ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static DEFINE_SPINLOCK(nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * There are two gpio ports, one for blinking and the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * for power. @port tells us if we're doing blinking or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * power control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Caller must hold nasgpio_gpio_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 port, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 gpio_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gpio_out = inl(nas_gpio_io_base + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) gpio_out |= (1<<led->gpio_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) gpio_out &= ~(1<<led->gpio_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) outl(gpio_out, nas_gpio_io_base + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void nasgpio_led_set_attr(struct led_classdev *led_cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 port, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spin_lock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __nasgpio_led_set_attr(led_cdev, port, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_unlock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 gpio_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spin_lock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) gpio_in = inl(nas_gpio_io_base + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_unlock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (gpio_in & (1<<led->gpio_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * There is actual brightness control in the hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * but it is via smbus commands and not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * in this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum led_brightness brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 setting = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (brightness >= LED_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) setting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Hold the lock across both operations. This ensures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * consistency so that both the "turn off blinking"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * and "turn light off" operations complete as a set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_lock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * LED class documentation asks that past blink state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * be disabled when brightness is turned to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (brightness == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int nasgpio_led_set_blink(struct led_classdev *led_cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long *delay_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long *delay_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 setting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!(*delay_on == 0 && *delay_off == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) !(*delay_on == 500 && *delay_off == 500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * These are very approximate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *delay_on = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *delay_off = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * already taken care of this, but we will do so in a non destructive manner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * so that we have what we need whether the BIOS did it or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int ich7_gpio_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 config_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 all_nas_led = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spin_lock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * We need to enable all of the GPIO lines used by the NAS box,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * so we will read the current Use Selection and add our usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * to it. This should be benign with regard to the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * BIOS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) config_data |= all_nas_led + NAS_RECOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * The LED GPIO outputs need to be configured for output, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * will ensure that all LED lines are cleared for output and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * RECOVERY line ready for input. This too should be benign with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * regard to BIOS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) config_data = inl(nas_gpio_io_base + GP_IO_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) config_data &= ~all_nas_led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) config_data |= NAS_RECOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outl(config_data, nas_gpio_io_base + GP_IO_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) config_data = inl(nas_gpio_io_base + GP_IO_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * In our final system, the BIOS will initialize the state of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * of the LEDs. For now, we turn them all off (or Low).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) config_data = inl(nas_gpio_io_base + GP_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * In our final system, the BIOS will initialize the blink state of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * of the LEDs. For now, we turn blink off for all of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) config_data = inl(nas_gpio_io_base + GPO_BLINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * At this moment, I am unsure if anything needs to happen with GPI_INV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) config_data = inl(nas_gpio_io_base + GPI_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_unlock(&nasgpio_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void ich7_lpc_cleanup(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * If we were given exclusive use of the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * I/O Address range, we must return it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (gp_gpio_resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_dbg(dev, ": Releasing GPIO I/O addresses\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gp_gpio_resource = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * so we can retrive the required operational information and prepare the GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct pci_dev *nas_gpio_pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int ich7_lpc_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 gc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) status = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&dev->dev, "pci_enable_device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) nas_gpio_pci_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) g_pm_io_base &= 0x00000ff80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status = pci_read_config_dword(dev, GPIO_CTRL, &gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!(GPIO_EN & gc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) status = -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "ERROR: The LPC GPIO Block has not been enabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (0 > status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_info(&dev->dev, "Unable to read GPIOBASE.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) nas_gpio_io_base &= 0x00000ffc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Insure that we have exclusive access to the GPIO I/O address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (NULL == gp_gpio_resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "ERROR Unable to register GPIO I/O addresses.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Initialize the GPIO for NAS/Home Server Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ich7_gpio_init(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ich7_lpc_cleanup(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void ich7_lpc_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ich7_lpc_cleanup(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * pci_driver structure passed to the PCI modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct pci_driver nas_gpio_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .id_table = ich7_lpc_pci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .probe = ich7_lpc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .remove = ich7_lpc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct led_classdev *get_classdev_for_led_nr(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct nasgpio_led *nas_led = &nasgpio_leds[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct led_classdev *led = &nas_led->led_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void set_power_light_amber_noblink(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct nasgpio_led *amber = get_led_named("power:amber:power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct nasgpio_led *blue = get_led_named("power:blue:power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!amber || !blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * LED_OFF implies disabling future blinking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_debug("setting blue off and amber on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static ssize_t nas_led_blink_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct led_classdev *led = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int blinking = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (nasgpio_led_get_attr(led, GPO_BLINK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) blinking = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return sprintf(buf, "%u\n", blinking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static ssize_t nas_led_blink_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct led_classdev *led = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long blink_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = kstrtoul(buf, 10, &blink_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) nasgpio_led_set_attr(led, GPO_BLINK, blink_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static DEVICE_ATTR(blink, 0644, nas_led_blink_show, nas_led_blink_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct attribute *nasgpio_led_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &dev_attr_blink.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ATTRIBUTE_GROUPS(nasgpio_led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int register_nasgpio_led(int led_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct led_classdev *led = get_classdev_for_led_nr(led_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) led->name = nas_led->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) led->brightness = LED_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (nasgpio_led_get_attr(led, GP_LVL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) led->brightness = LED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) led->brightness_set = nasgpio_led_set_brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) led->blink_set = nasgpio_led_set_blink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) led->groups = nasgpio_led_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = led_classdev_register(&nas_gpio_pci_dev->dev, led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void unregister_nasgpio_led(int led_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct led_classdev *led = get_classdev_for_led_nr(led_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) led_classdev_unregister(led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * module load/initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int __init nas_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int nr_devices = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) nr_devices = dmi_check_system(nas_led_whitelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (nodetect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pr_info("skipping hardware autodetection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pr_info("Please send 'dmidecode' output to dave@sr71.net\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) nr_devices++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (nr_devices <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pr_info("no LED devices found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pr_info("registering PCI driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = pci_register_driver(&nas_gpio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = register_nasgpio_led(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * When the system powers on, the BIOS leaves the power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * light blue and blinking. This will turn it solid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * amber once the driver is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) set_power_light_amber_noblink();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unregister_nasgpio_led(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pci_unregister_driver(&nas_gpio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * module unload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void __exit nas_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pr_info("Unregistering driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unregister_nasgpio_led(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pci_unregister_driver(&nas_gpio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) module_init(nas_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_exit(nas_gpio_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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