^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI LP8501 9 channel LED Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/leds-lp55xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "leds-lp55xx-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP8501_PROGRAM_LENGTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP8501_MAX_LEDS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP8501_REG_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP8501_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP8501_EXEC_M 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP8501_EXEC_ENG1_M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP8501_EXEC_ENG2_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP8501_EXEC_ENG3_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP8501_RUN_ENG1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP8501_RUN_ENG2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP8501_RUN_ENG3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP8501_REG_OP_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP8501_MODE_ENG1_M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP8501_MODE_ENG2_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP8501_MODE_ENG3_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP8501_LOAD_ENG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP8501_LOAD_ENG2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP8501_LOAD_ENG3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP8501_REG_PWR_CONFIG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP8501_PWR_CONFIG_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP8501_REG_LED_PWM_BASE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP8501_REG_LED_CURRENT_BASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP8501_REG_CONFIG 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP8501_PWM_PSAVE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP8501_AUTO_INC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP8501_PWR_SAVE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP8501_CP_AUTO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP8501_INT_CLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP8501_DEFAULT_CFG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (LP8501_PWM_PSAVE | LP8501_AUTO_INC | LP8501_PWR_SAVE | LP8501_CP_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP8501_REG_RESET 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP8501_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP8501_REG_PROG_PAGE_SEL 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP8501_PAGE_ENG1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP8501_PAGE_ENG2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP8501_PAGE_ENG3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LP8501_REG_PROG_MEM 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP8501_ENG1_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ((mode & LP8501_MODE_ENG1_M) == LP8501_LOAD_ENG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP8501_ENG2_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((mode & LP8501_MODE_ENG2_M) == LP8501_LOAD_ENG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LP8501_ENG3_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((mode & LP8501_MODE_ENG3_M) == LP8501_LOAD_ENG3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline void lp8501_wait_opmode_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void lp8501_set_led_current(struct lp55xx_led *led, u8 led_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) led->led_current = led_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) lp55xx_write(led->chip, LP8501_REG_LED_CURRENT_BASE + led->chan_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) led_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int lp8501_post_init_device(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 val = LP8501_DEFAULT_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = lp55xx_write(chip, LP8501_REG_ENABLE, LP8501_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Chip startup time is 500 us, 1 - 2 ms gives some margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (chip->pdata->clock_mode != LP55XX_CLOCK_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val |= LP8501_INT_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = lp55xx_write(chip, LP8501_REG_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Power selection for each output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return lp55xx_update_bits(chip, LP8501_REG_PWR_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LP8501_PWR_CONFIG_M, chip->pdata->pwr_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void lp8501_load_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const u8 mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [LP55XX_ENGINE_1] = LP8501_MODE_ENG1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [LP55XX_ENGINE_2] = LP8501_MODE_ENG2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [LP55XX_ENGINE_3] = LP8501_MODE_ENG3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const u8 val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [LP55XX_ENGINE_1] = LP8501_LOAD_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [LP55XX_ENGINE_2] = LP8501_LOAD_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [LP55XX_ENGINE_3] = LP8501_LOAD_ENG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const u8 page_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [LP55XX_ENGINE_1] = LP8501_PAGE_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [LP55XX_ENGINE_2] = LP8501_PAGE_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [LP55XX_ENGINE_3] = LP8501_PAGE_ENG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) lp55xx_update_bits(chip, LP8501_REG_OP_MODE, mask[idx], val[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) lp8501_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) lp55xx_write(chip, LP8501_REG_PROG_PAGE_SEL, page_sel[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void lp8501_stop_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) lp55xx_write(chip, LP8501_REG_OP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) lp8501_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void lp8501_turn_off_channels(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 0; i < LP8501_MAX_LEDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) lp55xx_write(chip, LP8501_REG_LED_PWM_BASE + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void lp8501_run_engine(struct lp55xx_chip *chip, bool start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 exec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* stop engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) lp8501_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) lp8501_turn_off_channels(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * To run the engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * operation mode and enable register should updated at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = lp55xx_read(chip, LP8501_REG_OP_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = lp55xx_read(chip, LP8501_REG_ENABLE, &exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* change operation mode to RUN only when each engine is loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (LP8501_ENG1_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mode = (mode & ~LP8501_MODE_ENG1_M) | LP8501_RUN_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) exec = (exec & ~LP8501_EXEC_ENG1_M) | LP8501_RUN_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (LP8501_ENG2_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mode = (mode & ~LP8501_MODE_ENG2_M) | LP8501_RUN_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) exec = (exec & ~LP8501_EXEC_ENG2_M) | LP8501_RUN_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (LP8501_ENG3_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mode = (mode & ~LP8501_MODE_ENG3_M) | LP8501_RUN_ENG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) exec = (exec & ~LP8501_EXEC_ENG3_M) | LP8501_RUN_ENG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) lp55xx_write(chip, LP8501_REG_OP_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) lp8501_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) lp55xx_update_bits(chip, LP8501_REG_ENABLE, LP8501_EXEC_M, exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int lp8501_update_program_memory(struct lp55xx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const u8 *data, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 pattern[LP8501_PROGRAM_LENGTH] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) char c[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int update_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* clear program memory before updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (i = 0; i < LP8501_PROGRAM_LENGTH; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) lp55xx_write(chip, LP8501_REG_PROG_MEM + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) while ((offset < size - 1) && (i < LP8501_PROGRAM_LENGTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* separate sscanfs because length is working only for %s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = sscanf(c, "%2x", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pattern[i] = (u8)cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) offset += nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Each instruction is 16bit long. Check that length is even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (i % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) update_size = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 0; i < update_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) lp55xx_write(chip, LP8501_REG_PROG_MEM + i, pattern[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&chip->cl->dev, "wrong pattern format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void lp8501_firmware_loaded(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const struct firmware *fw = chip->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (fw->size > LP8501_PROGRAM_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Program memory sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 1) set engine mode to "LOAD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * 2) write firmware data into program memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) lp8501_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) lp8501_update_program_memory(chip, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int lp8501_led_brightness(struct lp55xx_led *led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = lp55xx_write(chip, LP8501_REG_LED_PWM_BASE + led->chan_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) led->brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Chip specific configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct lp55xx_device_config lp8501_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .addr = LP8501_REG_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .val = LP8501_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .addr = LP8501_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .val = LP8501_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .max_channel = LP8501_MAX_LEDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .post_init_device = lp8501_post_init_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .brightness_fn = lp8501_led_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .set_led_current = lp8501_set_led_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .firmware_cb = lp8501_firmware_loaded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .run_engine = lp8501_run_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int lp8501_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct lp55xx_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct lp55xx_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct device_node *np = dev_of_node(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) chip->cfg = &lp8501_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pdata = lp55xx_of_populate_pdata(&client->dev, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(&client->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) led = devm_kcalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pdata->num_channels, sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) chip->cl = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) chip->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) i2c_set_clientdata(client, led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = lp55xx_init_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_info(&client->dev, "%s Programmable led chip found\n", id->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = lp55xx_register_leds(led, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = lp55xx_register_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&client->dev, "registering sysfs failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int lp8501_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct lp55xx_led *led = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) lp8501_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) lp55xx_unregister_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct i2c_device_id lp8501_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { "lp8501", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DEVICE_TABLE(i2c, lp8501_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct of_device_id of_lp8501_leds_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { .compatible = "ti,lp8501", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_DEVICE_TABLE(of, of_lp8501_leds_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct i2c_driver lp8501_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = "lp8501",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .of_match_table = of_match_ptr(of_lp8501_leds_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .probe = lp8501_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .remove = lp8501_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .id_table = lp8501_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_i2c_driver(lp8501_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("Texas Instruments LP8501 LED driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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