^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * LP5562 LED driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/leds-lp55xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "leds-lp55xx-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LP5562_PROGRAM_LENGTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP5562_MAX_LEDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* ENABLE Register 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP5562_REG_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP5562_EXEC_ENG1_M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP5562_EXEC_ENG2_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP5562_EXEC_ENG3_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP5562_EXEC_M 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP5562_MASTER_ENABLE 0x40 /* Chip master enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP5562_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP5562_EXEC_RUN 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP5562_ENABLE_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (LP5562_MASTER_ENABLE | LP5562_LOGARITHMIC_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP5562_ENABLE_RUN_PROGRAM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (LP5562_ENABLE_DEFAULT | LP5562_EXEC_RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* OPMODE Register 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP5562_REG_OP_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP5562_MODE_ENG1_M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP5562_MODE_ENG2_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP5562_MODE_ENG3_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP5562_LOAD_ENG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP5562_LOAD_ENG2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP5562_LOAD_ENG3 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP5562_RUN_ENG1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP5562_RUN_ENG2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP5562_RUN_ENG3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP5562_ENG1_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ((mode & LP5562_MODE_ENG1_M) == LP5562_LOAD_ENG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP5562_ENG2_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ((mode & LP5562_MODE_ENG2_M) == LP5562_LOAD_ENG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP5562_ENG3_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ((mode & LP5562_MODE_ENG3_M) == LP5562_LOAD_ENG3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* BRIGHTNESS Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP5562_REG_R_PWM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP5562_REG_G_PWM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP5562_REG_B_PWM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP5562_REG_W_PWM 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* CURRENT Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP5562_REG_R_CURRENT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP5562_REG_G_CURRENT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP5562_REG_B_CURRENT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP5562_REG_W_CURRENT 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* CONFIG Register 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LP5562_REG_CONFIG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP5562_PWM_HF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LP5562_PWRSAVE_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP5562_CLK_INT 0x01 /* Internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LP5562_DEFAULT_CFG (LP5562_PWM_HF | LP5562_PWRSAVE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* RESET Register 0Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP5562_REG_RESET 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LP5562_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* PROGRAM ENGINE Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LP5562_REG_PROG_MEM_ENG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LP5562_REG_PROG_MEM_ENG2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LP5562_REG_PROG_MEM_ENG3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* LEDMAP Register 70h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LP5562_REG_ENG_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LP5562_ENG_SEL_PWM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LP5562_ENG_FOR_RGB_M 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LP5562_ENG_SEL_RGB 0x1B /* R:ENG1, G:ENG2, B:ENG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LP5562_ENG_FOR_W_M 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LP5562_ENG1_FOR_W 0x40 /* W:ENG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LP5562_ENG2_FOR_W 0x80 /* W:ENG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LP5562_ENG3_FOR_W 0xC0 /* W:ENG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Program Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LP5562_CMD_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LP5562_CMD_LOAD 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LP5562_CMD_RUN 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LP5562_CMD_DIRECT 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LP5562_PATTERN_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void lp5562_wait_opmode_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* operation mode change needs to be longer than 153 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void lp5562_wait_enable_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* it takes more 488 us to update ENABLE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void lp5562_set_led_current(struct lp55xx_led *led, u8 led_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const u8 addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LP5562_REG_R_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LP5562_REG_G_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LP5562_REG_B_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LP5562_REG_W_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) led->led_current = led_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) lp55xx_write(led->chip, addr[led->chan_nr], led_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void lp5562_load_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const u8 mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [LP55XX_ENGINE_1] = LP5562_MODE_ENG1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [LP55XX_ENGINE_2] = LP5562_MODE_ENG2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [LP55XX_ENGINE_3] = LP5562_MODE_ENG3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const u8 val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [LP55XX_ENGINE_1] = LP5562_LOAD_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [LP55XX_ENGINE_2] = LP5562_LOAD_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [LP55XX_ENGINE_3] = LP5562_LOAD_ENG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) lp55xx_update_bits(chip, LP5562_REG_OP_MODE, mask[idx], val[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) lp5562_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void lp5562_stop_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lp5562_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void lp5562_run_engine(struct lp55xx_chip *chip, bool start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 exec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* stop engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) lp55xx_write(chip, LP5562_REG_ENABLE, LP5562_ENABLE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) lp5562_wait_enable_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) lp5562_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) lp5562_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * To run the engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * operation mode and enable register should updated at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = lp55xx_read(chip, LP5562_REG_OP_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = lp55xx_read(chip, LP5562_REG_ENABLE, &exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* change operation mode to RUN only when each engine is loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (LP5562_ENG1_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mode = (mode & ~LP5562_MODE_ENG1_M) | LP5562_RUN_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) exec = (exec & ~LP5562_EXEC_ENG1_M) | LP5562_RUN_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (LP5562_ENG2_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mode = (mode & ~LP5562_MODE_ENG2_M) | LP5562_RUN_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) exec = (exec & ~LP5562_EXEC_ENG2_M) | LP5562_RUN_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (LP5562_ENG3_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mode = (mode & ~LP5562_MODE_ENG3_M) | LP5562_RUN_ENG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) exec = (exec & ~LP5562_EXEC_ENG3_M) | LP5562_RUN_ENG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) lp55xx_write(chip, LP5562_REG_OP_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) lp5562_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) lp55xx_update_bits(chip, LP5562_REG_ENABLE, LP5562_EXEC_M, exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) lp5562_wait_enable_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int lp5562_update_firmware(struct lp55xx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const u8 *data, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 pattern[LP5562_PROGRAM_LENGTH] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const u8 addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [LP55XX_ENGINE_1] = LP5562_REG_PROG_MEM_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [LP55XX_ENGINE_2] = LP5562_REG_PROG_MEM_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [LP55XX_ENGINE_3] = LP5562_REG_PROG_MEM_ENG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) char c[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int program_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* clear program memory before updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; i < LP5562_PROGRAM_LENGTH; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) lp55xx_write(chip, addr[idx] + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) while ((offset < size - 1) && (i < LP5562_PROGRAM_LENGTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* separate sscanfs because length is working only for %s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = sscanf(c, "%2x", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pattern[i] = (u8)cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) offset += nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Each instruction is 16bit long. Check that length is even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (i % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) program_size = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < program_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) lp55xx_write(chip, addr[idx] + i, pattern[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(&chip->cl->dev, "wrong pattern format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void lp5562_firmware_loaded(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) const struct firmware *fw = chip->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * the firmware is encoded in ascii hex character, with 2 chars
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * per byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (fw->size > (LP5562_PROGRAM_LENGTH * 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Program memory sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 1) set engine mode to "LOAD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 2) write firmware data into program memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) lp5562_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) lp5562_update_firmware(chip, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int lp5562_post_init_device(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 cfg = LP5562_DEFAULT_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Set all PWMs to direct control mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) lp5562_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Update configuration for the clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!lp55xx_is_extclk_used(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cfg |= LP5562_CLK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = lp55xx_write(chip, LP5562_REG_CONFIG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Initialize all channels PWM to zero -> leds off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) lp55xx_write(chip, LP5562_REG_R_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) lp55xx_write(chip, LP5562_REG_G_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) lp55xx_write(chip, LP5562_REG_B_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) lp55xx_write(chip, LP5562_REG_W_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Set LED map as register PWM by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int lp5562_led_brightness(struct lp55xx_led *led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const u8 addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LP5562_REG_R_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) LP5562_REG_G_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LP5562_REG_B_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) LP5562_REG_W_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = lp55xx_write(chip, addr[led->chan_nr], led->brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void lp5562_write_program_memory(struct lp55xx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 base, const u8 *rgb, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!rgb || size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) lp55xx_write(chip, base + i, *(rgb + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) lp55xx_write(chip, base + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) lp55xx_write(chip, base + i + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* check the size of program count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline bool _is_pc_overflow(struct lp55xx_predef_pattern *ptn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ptn->size_r >= LP5562_PROGRAM_LENGTH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ptn->size_g >= LP5562_PROGRAM_LENGTH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ptn->size_b >= LP5562_PROGRAM_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int lp5562_run_predef_led_pattern(struct lp55xx_chip *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct lp55xx_predef_pattern *ptn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (mode == LP5562_PATTERN_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) lp5562_run_engine(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ptn = chip->pdata->patterns + (mode - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!ptn || _is_pc_overflow(ptn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(&chip->cl->dev, "invalid pattern data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) lp5562_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Set LED map as RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Load engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = LP55XX_ENGINE_1; i <= LP55XX_ENGINE_3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) chip->engine_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) lp5562_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Clear program registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG1 + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG2 + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG3 + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Program engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ptn->r, ptn->size_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ptn->g, ptn->size_g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ptn->b, ptn->size_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Run engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lp5562_run_engine(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static ssize_t lp5562_store_pattern(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct lp55xx_predef_pattern *ptn = chip->pdata->patterns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int num_patterns = chip->pdata->num_patterns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = kstrtoul(buf, 0, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (mode > num_patterns || !ptn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = lp5562_run_predef_led_pattern(chip, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static ssize_t lp5562_store_engine_mux(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* LED map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * R ... Engine 1 (fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * G ... Engine 2 (fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * B ... Engine 3 (fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * W ... Engine 1 or 2 or 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (sysfs_streq(buf, "RGB")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mask = LP5562_ENG_FOR_RGB_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) val = LP5562_ENG_SEL_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if (sysfs_streq(buf, "W")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mask = LP5562_ENG_FOR_W_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case LP55XX_ENGINE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val = LP5562_ENG1_FOR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case LP55XX_ENGINE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) val = LP5562_ENG2_FOR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case LP55XX_ENGINE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val = LP5562_ENG3_FOR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "choose RGB or W\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) lp55xx_update_bits(chip, LP5562_REG_ENG_SEL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static LP55XX_DEV_ATTR_WO(led_pattern, lp5562_store_pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static LP55XX_DEV_ATTR_WO(engine_mux, lp5562_store_engine_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct attribute *lp5562_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &dev_attr_led_pattern.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &dev_attr_engine_mux.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct attribute_group lp5562_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .attrs = lp5562_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Chip specific configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static struct lp55xx_device_config lp5562_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .max_channel = LP5562_MAX_LEDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .addr = LP5562_REG_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .val = LP5562_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .enable = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .addr = LP5562_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .val = LP5562_ENABLE_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .post_init_device = lp5562_post_init_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .set_led_current = lp5562_set_led_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .brightness_fn = lp5562_led_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .run_engine = lp5562_run_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .firmware_cb = lp5562_firmware_loaded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .dev_attr_group = &lp5562_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int lp5562_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct lp55xx_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct lp55xx_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct device_node *np = dev_of_node(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) chip->cfg = &lp5562_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdata = lp55xx_of_populate_pdata(&client->dev, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(&client->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) led = devm_kcalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pdata->num_channels, sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) chip->cl = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) chip->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) i2c_set_clientdata(client, led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = lp55xx_init_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = lp55xx_register_leds(led, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = lp55xx_register_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(&client->dev, "registering sysfs failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int lp5562_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct lp55xx_led *led = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) lp5562_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) lp55xx_unregister_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct i2c_device_id lp5562_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { "lp5562", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_DEVICE_TABLE(i2c, lp5562_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct of_device_id of_lp5562_leds_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { .compatible = "ti,lp5562", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_DEVICE_TABLE(of, of_lp5562_leds_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct i2c_driver lp5562_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = "lp5562",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .of_match_table = of_match_ptr(of_lp5562_leds_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .probe = lp5562_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .remove = lp5562_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .id_table = lp5562_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) module_i2c_driver(lp5562_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_DESCRIPTION("Texas Instruments LP5562 LED Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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