^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * LP5521 LED chip driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/leds-lp55xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "leds-lp55xx-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP5521_PROGRAM_LENGTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP5521_MAX_LEDS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP5521_CMD_DIRECT 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP5521_REG_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP5521_REG_OP_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP5521_REG_R_PWM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP5521_REG_G_PWM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP5521_REG_B_PWM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP5521_REG_R_CURRENT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP5521_REG_G_CURRENT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP5521_REG_B_CURRENT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP5521_REG_CONFIG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP5521_REG_STATUS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP5521_REG_RESET 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP5521_REG_R_PROG_MEM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP5521_REG_G_PROG_MEM 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP5521_REG_B_PROG_MEM 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Base register to set LED current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP5521_REG_LED_CURRENT_BASE LP5521_REG_R_CURRENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Base register to set the brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP5521_REG_LED_PWM_BASE LP5521_REG_R_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Bits in ENABLE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP5521_MASTER_ENABLE 0x40 /* Chip master enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP5521_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP5521_EXEC_RUN 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP5521_ENABLE_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (LP5521_MASTER_ENABLE | LP5521_LOGARITHMIC_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP5521_ENABLE_RUN_PROGRAM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (LP5521_ENABLE_DEFAULT | LP5521_EXEC_RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* CONFIG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP5521_PWM_HF 0x40 /* PWM: 0 = 256Hz, 1 = 558Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP5521_PWRSAVE_EN 0x20 /* 1 = Power save mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP5521_CP_MODE_OFF 0 /* Charge pump (CP) off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP5521_CP_MODE_BYPASS 8 /* CP forced to bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP5521_CP_MODE_1X5 0x10 /* CP forced to 1.5x mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP5521_CP_MODE_AUTO 0x18 /* Automatic mode selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP5521_R_TO_BATT 0x04 /* R out: 0 = CP, 1 = Vbat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP5521_CLK_INT 0x01 /* Internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP5521_DEFAULT_CFG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (LP5521_PWM_HF | LP5521_PWRSAVE_EN | LP5521_CP_MODE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP5521_EXT_CLK_USED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* default R channel current register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LP5521_REG_R_CURR_DEFAULT 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Reset register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP5521_RESET 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Program Memory Operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LP5521_MODE_R_M 0x30 /* Operation Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LP5521_MODE_G_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LP5521_MODE_B_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LP5521_LOAD_R 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LP5521_LOAD_G 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LP5521_LOAD_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LP5521_R_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ((mode & LP5521_MODE_R_M) == LP5521_LOAD_R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LP5521_G_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ((mode & LP5521_MODE_G_M) == LP5521_LOAD_G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LP5521_B_IS_LOADING(mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ((mode & LP5521_MODE_B_M) == LP5521_LOAD_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LP5521_EXEC_R_M 0x30 /* Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LP5521_EXEC_G_M 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LP5521_EXEC_B_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LP5521_EXEC_M 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LP5521_RUN_R 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LP5521_RUN_G 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LP5521_RUN_B 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void lp5521_wait_opmode_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* operation mode change needs to be longer than 153 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void lp5521_wait_enable_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* it takes more 488 us to update ENABLE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void lp5521_set_led_current(struct lp55xx_led *led, u8 led_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) led->led_current = led_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) lp55xx_write(led->chip, LP5521_REG_LED_CURRENT_BASE + led->chan_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) led_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void lp5521_load_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const u8 mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [LP55XX_ENGINE_1] = LP5521_MODE_R_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [LP55XX_ENGINE_2] = LP5521_MODE_G_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [LP55XX_ENGINE_3] = LP5521_MODE_B_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const u8 val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [LP55XX_ENGINE_1] = LP5521_LOAD_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [LP55XX_ENGINE_2] = LP5521_LOAD_G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [LP55XX_ENGINE_3] = LP5521_LOAD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], val[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) lp5521_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void lp5521_stop_all_engines(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) lp55xx_write(chip, LP5521_REG_OP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) lp5521_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void lp5521_stop_engine(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const u8 mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [LP55XX_ENGINE_1] = LP5521_MODE_R_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [LP55XX_ENGINE_2] = LP5521_MODE_G_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [LP55XX_ENGINE_3] = LP5521_MODE_B_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) lp5521_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void lp5521_run_engine(struct lp55xx_chip *chip, bool start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 exec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* stop engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) lp5521_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) lp55xx_write(chip, LP5521_REG_OP_MODE, LP5521_CMD_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) lp5521_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * To run the engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * operation mode and enable register should updated at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = lp55xx_read(chip, LP5521_REG_OP_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = lp55xx_read(chip, LP5521_REG_ENABLE, &exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* change operation mode to RUN only when each engine is loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (LP5521_R_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mode = (mode & ~LP5521_MODE_R_M) | LP5521_RUN_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) exec = (exec & ~LP5521_EXEC_R_M) | LP5521_RUN_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (LP5521_G_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mode = (mode & ~LP5521_MODE_G_M) | LP5521_RUN_G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) exec = (exec & ~LP5521_EXEC_G_M) | LP5521_RUN_G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (LP5521_B_IS_LOADING(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mode = (mode & ~LP5521_MODE_B_M) | LP5521_RUN_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) exec = (exec & ~LP5521_EXEC_B_M) | LP5521_RUN_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) lp55xx_write(chip, LP5521_REG_OP_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lp5521_wait_opmode_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) lp55xx_update_bits(chip, LP5521_REG_ENABLE, LP5521_EXEC_M, exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) lp5521_wait_enable_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int lp5521_update_program_memory(struct lp55xx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const u8 *data, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum lp55xx_engine_index idx = chip->engine_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 pattern[LP5521_PROGRAM_LENGTH] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const u8 addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [LP55XX_ENGINE_1] = LP5521_REG_R_PROG_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [LP55XX_ENGINE_2] = LP5521_REG_G_PROG_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [LP55XX_ENGINE_3] = LP5521_REG_B_PROG_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) char c[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) while ((offset < size - 1) && (i < LP5521_PROGRAM_LENGTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* separate sscanfs because length is working only for %s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = sscanf(c, "%2x", &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pattern[i] = (u8)cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) offset += nrchars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Each instruction is 16bit long. Check that length is even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (i % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < LP5521_PROGRAM_LENGTH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = lp55xx_write(chip, addr[idx] + i, pattern[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(&chip->cl->dev, "wrong pattern format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void lp5521_firmware_loaded(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const struct firmware *fw = chip->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (fw->size > LP5521_PROGRAM_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Program memory sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * 1) set engine mode to "LOAD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * 2) write firmware data into program memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) lp5521_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) lp5521_update_program_memory(chip, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int lp5521_post_init_device(struct lp55xx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Make sure that the chip is reset by reading back the r channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * current reg. This is dummy read is required on some platforms -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * otherwise further access to the R G B channels in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * LP5521_REG_ENABLE register will not have any effect - strange!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = lp55xx_read(chip, LP5521_REG_R_CURRENT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&chip->cl->dev, "error in resetting chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (val != LP5521_REG_R_CURR_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(&chip->cl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "unexpected data in register (expected 0x%x got 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LP5521_REG_R_CURR_DEFAULT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Set all PWMs to direct control mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = lp55xx_write(chip, LP5521_REG_OP_MODE, LP5521_CMD_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Update configuration for the clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) val = LP5521_DEFAULT_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!lp55xx_is_extclk_used(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val |= LP5521_CLK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = lp55xx_write(chip, LP5521_REG_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Initialize all channels PWM to zero -> leds off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) lp55xx_write(chip, LP5521_REG_R_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) lp55xx_write(chip, LP5521_REG_G_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) lp55xx_write(chip, LP5521_REG_B_PWM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Set engines are set to run state when OP_MODE enables engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = lp55xx_write(chip, LP5521_REG_ENABLE, LP5521_ENABLE_RUN_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) lp5521_wait_enable_done();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int lp5521_run_selftest(struct lp55xx_chip *chip, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct lp55xx_platform_data *pdata = chip->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = lp55xx_read(chip, LP5521_REG_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pdata->clock_mode != LP55XX_CLOCK_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Check that ext clock is really in use if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if ((status & LP5521_EXT_CLK_USED) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int lp5521_multicolor_brightness(struct lp55xx_led *led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = 0; i < led->mc_cdev.num_colors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = lp55xx_write(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) LP5521_REG_LED_PWM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) led->mc_cdev.subled_info[i].channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) led->mc_cdev.subled_info[i].brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int lp5521_led_brightness(struct lp55xx_led *led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = lp55xx_write(chip, LP5521_REG_LED_PWM_BASE + led->chan_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) led->brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static ssize_t show_engine_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) char *buf, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case LP55XX_ENGINE_RUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return sprintf(buf, "run\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case LP55XX_ENGINE_LOAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return sprintf(buf, "load\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case LP55XX_ENGINE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return sprintf(buf, "disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) show_mode(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) show_mode(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) show_mode(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static ssize_t store_engine_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const char *buf, size_t len, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct lp55xx_engine *engine = &chip->engines[nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) chip->engine_idx = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!strncmp(buf, "run", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) lp5521_run_engine(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) engine->mode = LP55XX_ENGINE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else if (!strncmp(buf, "load", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) lp5521_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) lp5521_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) engine->mode = LP55XX_ENGINE_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else if (!strncmp(buf, "disabled", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) lp5521_stop_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) engine->mode = LP55XX_ENGINE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) store_mode(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) store_mode(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) store_mode(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static ssize_t store_engine_load(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const char *buf, size_t len, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chip->engine_idx = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) lp5521_load_engine(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = lp5521_update_program_memory(chip, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) store_load(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) store_load(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) store_load(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static ssize_t lp5521_selftest(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = lp5521_run_selftest(chip, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return scnprintf(buf, PAGE_SIZE, "%s\n", ret ? "FAIL" : "OK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* device attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static LP55XX_DEV_ATTR_RW(engine1_mode, show_engine1_mode, store_engine1_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static LP55XX_DEV_ATTR_RW(engine2_mode, show_engine2_mode, store_engine2_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static LP55XX_DEV_ATTR_RW(engine3_mode, show_engine3_mode, store_engine3_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static LP55XX_DEV_ATTR_WO(engine1_load, store_engine1_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static LP55XX_DEV_ATTR_WO(engine2_load, store_engine2_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static LP55XX_DEV_ATTR_WO(engine3_load, store_engine3_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static LP55XX_DEV_ATTR_RO(selftest, lp5521_selftest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct attribute *lp5521_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &dev_attr_engine1_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &dev_attr_engine2_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &dev_attr_engine3_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &dev_attr_engine1_load.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &dev_attr_engine2_load.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &dev_attr_engine3_load.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &dev_attr_selftest.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct attribute_group lp5521_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .attrs = lp5521_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Chip specific configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct lp55xx_device_config lp5521_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .reset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .addr = LP5521_REG_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .val = LP5521_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .enable = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .addr = LP5521_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .val = LP5521_ENABLE_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .max_channel = LP5521_MAX_LEDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .post_init_device = lp5521_post_init_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .brightness_fn = lp5521_led_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .multicolor_brightness_fn = lp5521_multicolor_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .set_led_current = lp5521_set_led_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .firmware_cb = lp5521_firmware_loaded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .run_engine = lp5521_run_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .dev_attr_group = &lp5521_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int lp5521_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct lp55xx_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct lp55xx_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct device_node *np = dev_of_node(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) chip->cfg = &lp5521_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pdata = lp55xx_of_populate_pdata(&client->dev, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(&client->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) led = devm_kcalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pdata->num_channels, sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) chip->cl = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) chip->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i2c_set_clientdata(client, led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = lp55xx_init_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_info(&client->dev, "%s programmable led chip found\n", id->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = lp55xx_register_leds(led, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = lp55xx_register_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(&client->dev, "registering sysfs failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int lp5521_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct lp55xx_led *led = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct lp55xx_chip *chip = led->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) lp5521_stop_all_engines(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) lp55xx_unregister_sysfs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) lp55xx_deinit_device(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct i2c_device_id lp5521_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { "lp5521", 0 }, /* Three channel chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_DEVICE_TABLE(i2c, lp5521_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct of_device_id of_lp5521_leds_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .compatible = "national,lp5521", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_DEVICE_TABLE(of, of_lp5521_leds_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct i2c_driver lp5521_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "lp5521",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .of_match_table = of_match_ptr(of_lp5521_leds_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .probe = lp5521_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .remove = lp5521_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .id_table = lp5521_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) module_i2c_driver(lp5521_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_AUTHOR("Mathias Nyman, Yuri Zaporozhets, Samu Onkalo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_AUTHOR("Milo Kim <milo.kim@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_DESCRIPTION("LP5521 LED engine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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