^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Winbond W6692 specific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Specifications of W6692 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define W_D_RFIFO 0x00 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define W_D_XFIFO 0x04 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define W_D_CMDR 0x08 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define W_D_MODE 0x0c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define W_D_TIMR 0x10 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define W_ISTA 0x14 /* R_clr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define W_IMASK 0x18 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define W_D_EXIR 0x1c /* R_clr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define W_D_EXIM 0x20 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define W_D_STAR 0x24 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define W_D_RSTA 0x28 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define W_D_SAM 0x2c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define W_D_SAP1 0x30 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define W_D_SAP2 0x34 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define W_D_TAM 0x38 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define W_D_TEI1 0x3c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define W_D_TEI2 0x40 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define W_D_RBCH 0x44 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define W_D_RBCL 0x48 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define W_TIMR2 0x4c /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define W_L1_RC 0x50 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define W_D_CTL 0x54 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define W_CIR 0x58 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define W_CIX 0x5c /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define W_SQR 0x60 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define W_SQX 0x64 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define W_PCTL 0x68 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define W_MOR 0x6c /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define W_MOX 0x70 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define W_MOSR 0x74 /* R_clr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define W_MOCR 0x78 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define W_GCR 0x7c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define W_B_RFIFO 0x80 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define W_B_XFIFO 0x84 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define W_B_CMDR 0x88 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define W_B_MODE 0x8c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define W_B_EXIR 0x90 /* R_clr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define W_B_EXIM 0x94 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define W_B_STAR 0x98 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define W_B_ADM1 0x9c /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define W_B_ADM2 0xa0 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define W_B_ADR1 0xa4 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define W_B_ADR2 0xa8 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define W_B_RBCL 0xac /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define W_B_RBCH 0xb0 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define W_XADDR 0xf4 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define W_XDATA 0xf8 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define W_EPCTL 0xfc /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* W6692 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define W_D_CMDR_XRST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define W_D_CMDR_XME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define W_D_CMDR_XMS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define W_D_CMDR_STT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define W_D_CMDR_RRST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define W_D_CMDR_RACK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define W_D_MODE_RLP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define W_D_MODE_DLP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define W_D_MODE_MFD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define W_D_MODE_TEE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define W_D_MODE_TMS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define W_D_MODE_RACT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define W_D_MODE_MMS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define W_INT_B2_EXI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define W_INT_B1_EXI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define W_INT_D_EXI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define W_INT_XINT0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define W_INT_XINT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define W_INT_D_XFR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define W_INT_D_RME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define W_INT_D_RMR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define W_D_EXI_WEXP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define W_D_EXI_TEXP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define W_D_EXI_ISC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define W_D_EXI_MOC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define W_D_EXI_TIN2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define W_D_EXI_XCOL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define W_D_EXI_XDUN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define W_D_EXI_RDOV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define W_D_STAR_DRDY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define W_D_STAR_XBZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define W_D_STAR_XDOW 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define W_D_RSTA_RMB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define W_D_RSTA_CRCE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define W_D_RSTA_RDOV 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define W_D_CTL_SRST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define W_CIR_SCC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define W_CIR_ICC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define W_CIR_COD_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define W_PCTL_PCX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define W_PCTL_XMODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define W_PCTL_OE0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define W_PCTL_OE1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define W_PCTL_OE2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define W_PCTL_OE3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define W_PCTL_OE4 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define W_PCTL_OE5 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define W_B_CMDR_XRST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define W_B_CMDR_XME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define W_B_CMDR_XMS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define W_B_CMDR_RACT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define W_B_CMDR_RRST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define W_B_CMDR_RACK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define W_B_MODE_FTS0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define W_B_MODE_FTS1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define W_B_MODE_SW56 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define W_B_MODE_BSW0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define W_B_MODE_BSW1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define W_B_MODE_EPCM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define W_B_MODE_ITF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define W_B_MODE_MMS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define W_B_EXI_XDUN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define W_B_EXI_XFR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define W_B_EXI_RDOV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define W_B_EXI_RME 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define W_B_EXI_RMR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define W_B_STAR_XBZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define W_B_STAR_XDOW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define W_B_STAR_RMB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define W_B_STAR_CRCE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define W_B_STAR_RDOV 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define W_B_RBCH_LOV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* W6692 Layer1 commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define W_L1CMD_ECK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define W_L1CMD_RST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define W_L1CMD_SCP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define W_L1CMD_SSP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define W_L1CMD_AR8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define W_L1CMD_AR10 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define W_L1CMD_EAL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define W_L1CMD_DRC 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* W6692 Layer1 indications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define W_L1IND_CE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define W_L1IND_DRD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define W_L1IND_LD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define W_L1IND_ARD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define W_L1IND_TI 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define W_L1IND_ATI 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define W_L1IND_AI8 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define W_L1IND_AI10 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define W_L1IND_CD 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* FIFO thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define W_D_FIFO_THRESH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define W_B_FIFO_THRESH 64
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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