^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w6692.c mISDN driver for Winbond w6692 based cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author Karsten Keil <kkeil@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mISDNhw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "w6692.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define W6692_REV "2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DBUSY_TIMER_VALUE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) W6692_ASUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) W6692_WINBOND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) W6692_USR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* private data in the PCI devices list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct w6692map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u_int subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct w6692map w6692_map[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {W6692_ASUS, "Dynalink/AsusCom IS64PH"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {W6692_WINBOND, "Winbond W6692"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {W6692_USR, "USR W6692"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_DEVICE_ID_USR_6692 0x3409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct w6692_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct bchannel bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 b_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct w6692_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) char name[MISDN_MAX_IDLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 irqcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 fmask; /* feature mask - bit set per card nr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spinlock_t lock; /* hw lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 xaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 xdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct w6692_ch bc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct dchannel dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) char log[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static LIST_HEAD(Cards);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static DEFINE_RWLOCK(card_lock); /* protect Cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int w6692_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static u32 led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static u32 pots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _set_debug(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) card->dch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) card->bc[0].bch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) card->bc[1].bch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) set_debug(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct w6692_hw *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = param_set_uint(val, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) read_lock(&card_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) list_for_each_entry(card, &Cards, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) _set_debug(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) read_unlock(&card_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_AUTHOR("Karsten Keil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_VERSION(W6692_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_PARM_DESC(debug, "W6692 debug mask");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) module_param(led, uint, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_PARM_DESC(led, "W6692 LED support bitmask (one bit per card)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) module_param(pots, uint, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_PARM_DESC(pots, "W6692 POTS support bitmask (one bit per card)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ReadW6692(struct w6692_hw *card, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return inb(card->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) WriteW6692(struct w6692_hw *card, u8 offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) outb(value, card->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ReadW6692B(struct w6692_ch *bc, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return inb(bc->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WriteW6692B(struct w6692_ch *bc, u8 offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) outb(value, bc->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enable_hwirq(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) WriteW6692(card, W_IMASK, card->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) disable_hwirq(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) WriteW6692(card, W_IMASK, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char *W6692Ver[] = {"V00", "V01", "V10", "V11"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) W6692Version(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = ReadW6692(card, W_D_RBCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pr_notice("%s: Winbond W6692 version: %s\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) W6692Ver[(val >> 6) & 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) w6692_led_handler(struct w6692_hw *card, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if ((!(card->fmask & led)) || card->subtype == W6692_USR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) card->xdata &= 0xfb; /* LED ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) WriteW6692(card, W_XDATA, card->xdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) card->xdata |= 0x04; /* LED OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WriteW6692(card, W_XDATA, card->xdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ph_command(struct w6692_hw *card, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pr_debug("%s: ph_command %x\n", card->name, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) WriteW6692(card, W_CIX, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) W6692_new_ph(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (card->state == W_L1CMD_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ph_command(card, W_L1CMD_DRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) schedule_event(&card->dch, FLG_PHCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) W6692_ph_bh(struct dchannel *dch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct w6692_hw *card = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) switch (card->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case W_L1CMD_RST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dch->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) l1_event(dch->l1, HW_RESET_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case W_L1IND_CD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dch->state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) l1_event(dch->l1, HW_DEACT_CNF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case W_L1IND_DRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dch->state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) l1_event(dch->l1, HW_DEACT_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case W_L1IND_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dch->state = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) l1_event(dch->l1, HW_POWERUP_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case W_L1IND_LD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (dch->state <= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dch->state = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) l1_event(dch->l1, ANYSIGNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dch->state = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) l1_event(dch->l1, LOSTFRAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case W_L1IND_ARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dch->state = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) l1_event(dch->l1, INFO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case W_L1IND_AI8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dch->state = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) l1_event(dch->l1, INFO4_P8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case W_L1IND_AI10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dch->state = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) l1_event(dch->l1, INFO4_P10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_debug("%s: TE unknown state %02x dch state %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) card->name, card->state, dch->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_debug("%s: TE newstate %02x\n", card->name, dch->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) W6692_empty_Dfifo(struct w6692_hw *card, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct dchannel *dch = &card->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pr_debug("%s: empty_Dfifo %d\n", card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dch->rx_skb = mI_alloc_skb(card->dch.maxlen, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pr_info("%s: D receive out of memory\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if ((dch->rx_skb->len + count) >= dch->maxlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_debug("%s: empty_Dfifo overrun %d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dch->rx_skb->len + count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ptr = skb_put(dch->rx_skb, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) insb(card->addr + W_D_RFIFO, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (debug & DEBUG_HW_DFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) snprintf(card->log, 63, "D-recv %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) W6692_fill_Dfifo(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct dchannel *dch = &card->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 cmd = W_D_CMDR_XMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pr_debug("%s: fill_Dfifo\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!dch->tx_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) count = dch->tx_skb->len - dch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (count > W_D_FIFO_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) count = W_D_FIFO_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cmd |= W_D_CMDR_XME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ptr = dch->tx_skb->data + dch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dch->tx_idx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) outsb(card->addr + W_D_XFIFO, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) WriteW6692(card, W_D_CMDR, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (test_and_set_bit(FLG_BUSY_TIMER, &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pr_debug("%s: fill_Dfifo dbusytimer running\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) del_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dch->timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) add_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (debug & DEBUG_HW_DFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) snprintf(card->log, 63, "D-send %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) d_retransmit(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct dchannel *dch = &card->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) del_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dchannel_sched_event(dch, D_CLEARBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (test_bit(FLG_TX_BUSY, &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Restart frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } else if (dch->tx_skb) { /* should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pr_info("%s: %s without TX_BUSY\n", card->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) test_and_set_bit(FLG_TX_BUSY, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pr_info("%s: XDU no TX_BUSY\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (get_next_dframe(dch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) handle_rxD(struct w6692_hw *card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) stat = ReadW6692(card, W_D_RSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (stat & (W_D_RSTA_RDOV | W_D_RSTA_CRCE | W_D_RSTA_RMB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (stat & W_D_RSTA_RDOV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_debug("%s: D-channel RDOV\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) card->dch.err_rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (stat & W_D_RSTA_CRCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pr_debug("%s: D-channel CRC error\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) card->dch.err_crc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (stat & W_D_RSTA_RMB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pr_debug("%s: D-channel ABORT\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) card->dch.err_rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_kfree_skb(card->dch.rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) card->dch.rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) count = ReadW6692(card, W_D_RBCL) & (W_D_FIFO_THRESH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) count = W_D_FIFO_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) W6692_empty_Dfifo(card, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) recv_Dchannel(&card->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) handle_txD(struct w6692_hw *card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (test_and_clear_bit(FLG_BUSY_TIMER, &card->dch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) del_timer(&card->dch.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (card->dch.tx_skb && card->dch.tx_idx < card->dch.tx_skb->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_kfree_skb(card->dch.tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (get_next_dframe(&card->dch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) handle_statusD(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct dchannel *dch = &card->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 exval, v1, cir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) exval = ReadW6692(card, W_D_EXIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pr_debug("%s: D_EXIR %02x\n", card->name, exval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (exval & (W_D_EXI_XDUN | W_D_EXI_XCOL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Transmit underrun/collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_debug("%s: D-channel underrun/collision\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dch->err_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) d_retransmit(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (exval & W_D_EXI_RDOV) { /* RDOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_debug("%s: D-channel RDOV\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (exval & W_D_EXI_TIN2) /* TIN2 - never */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_debug("%s: spurious TIN2 interrupt\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (exval & W_D_EXI_MOC) { /* MOC - not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) v1 = ReadW6692(card, W_MOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pr_debug("%s: spurious MOC interrupt MOSR %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) card->name, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (exval & W_D_EXI_ISC) { /* ISC - Level1 change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cir = ReadW6692(card, W_CIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pr_debug("%s: ISC CIR %02X\n", card->name, cir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (cir & W_CIR_ICC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) v1 = cir & W_CIR_COD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pr_debug("%s: ph_state_change %x -> %x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dch->state, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) card->state = v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (card->fmask & led) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (v1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case W_L1IND_AI8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case W_L1IND_AI10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) w6692_led_handler(card, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) w6692_led_handler(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) W6692_new_ph(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (cir & W_CIR_SCC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) v1 = ReadW6692(card, W_SQR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pr_debug("%s: SCC SQR %02X\n", card->name, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (exval & W_D_EXI_WEXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pr_debug("%s: spurious WEXP interrupt!\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (exval & W_D_EXI_TEXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_debug("%s: spurious TEXP interrupt!\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) W6692_empty_Bfifo(struct w6692_ch *wch, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct w6692_hw *card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pr_debug("%s: empty_Bfifo %d\n", card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (unlikely(wch->bch.state == ISDN_P_NONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_debug("%s: empty_Bfifo ISDN_P_NONE\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (wch->bch.rx_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) skb_trim(wch->bch.rx_skb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) wch->bch.dropcnt += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) maxlen = bchannel_get_rxbuf(&wch->bch, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (maxlen < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (wch->bch.rx_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) skb_trim(wch->bch.rx_skb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pr_warn("%s.B%d: No bufferspace for %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) card->name, wch->bch.nr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ptr = skb_put(wch->bch.rx_skb, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) insb(wch->addr + W_B_RFIFO, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (debug & DEBUG_HW_DFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snprintf(card->log, 63, "B%1d-recv %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) wch->bch.nr, card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) W6692_fill_Bfifo(struct w6692_ch *wch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct w6692_hw *card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int count, fillempty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 *ptr, cmd = W_B_CMDR_RACT | W_B_CMDR_XMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pr_debug("%s: fill Bfifo\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!wch->bch.tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!test_bit(FLG_TX_EMPTY, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ptr = wch->bch.fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) count = W_B_FIFO_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fillempty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) count = wch->bch.tx_skb->len - wch->bch.tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ptr = wch->bch.tx_skb->data + wch->bch.tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (count > W_B_FIFO_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) count = W_B_FIFO_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else if (test_bit(FLG_HDLC, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cmd |= W_B_CMDR_XME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pr_debug("%s: fill Bfifo%d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) count, wch->bch.tx_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) wch->bch.tx_idx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (fillempty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) while (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) outsb(wch->addr + W_B_XFIFO, ptr, MISDN_BCH_FILL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) count -= MISDN_BCH_FILL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) outsb(wch->addr + W_B_XFIFO, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) WriteW6692B(wch, W_B_CMDR, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if ((debug & DEBUG_HW_BFIFO) && !fillempty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) snprintf(card->log, 63, "B%1d-send %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) wch->bch.nr, card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) setvolume(struct w6692_ch *wch, int mic, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct w6692_hw *card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u16 *vol = (u16 *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if ((!(card->fmask & pots)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (skb->len < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (*vol > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val = *vol & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = 7 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (mic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) card->xaddr &= 0xc7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) card->xaddr &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) card->xaddr |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) WriteW6692(card, W_XADDR, card->xaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) enable_pots(struct w6692_ch *wch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct w6692_hw *card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if ((!(card->fmask & pots)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) wch->b_mode |= W_B_MODE_EPCM | W_B_MODE_BSW0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) WriteW6692B(wch, W_B_MODE, wch->b_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) card->pctl |= ((wch->bch.nr & 2) ? W_PCTL_PCX : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) WriteW6692(card, W_PCTL, card->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) disable_pots(struct w6692_ch *wch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct w6692_hw *card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!(card->fmask & pots))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) wch->b_mode &= ~(W_B_MODE_EPCM | W_B_MODE_BSW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) WriteW6692B(wch, W_B_MODE, wch->b_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) w6692_mode(struct w6692_ch *wch, u32 pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct w6692_hw *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) card = wch->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pr_debug("%s: B%d protocol %x-->%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) wch->bch.nr, wch->bch.state, pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (pr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case ISDN_P_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if ((card->fmask & pots) && (wch->b_mode & W_B_MODE_EPCM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) disable_pots(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) wch->b_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mISDN_clear_bchannel(&wch->bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) WriteW6692B(wch, W_B_MODE, wch->b_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) test_and_clear_bit(FLG_HDLC, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) test_and_clear_bit(FLG_TRANSPARENT, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case ISDN_P_B_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) wch->b_mode = W_B_MODE_MMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) WriteW6692B(wch, W_B_MODE, wch->b_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) WriteW6692B(wch, W_B_EXIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) test_and_set_bit(FLG_TRANSPARENT, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case ISDN_P_B_HDLC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) wch->b_mode = W_B_MODE_ITF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) WriteW6692B(wch, W_B_MODE, wch->b_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) WriteW6692B(wch, W_B_ADM1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) WriteW6692B(wch, W_B_ADM2, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) WriteW6692B(wch, W_B_EXIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) test_and_set_bit(FLG_HDLC, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pr_info("%s: protocol %x not known\n", card->name, pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -ENOPROTOOPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) wch->bch.state = pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) send_next(struct w6692_ch *wch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (wch->bch.tx_skb && wch->bch.tx_idx < wch->bch.tx_skb->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) W6692_fill_Bfifo(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_kfree_skb(wch->bch.tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (get_next_bframe(&wch->bch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) W6692_fill_Bfifo(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) test_and_clear_bit(FLG_TX_EMPTY, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else if (test_bit(FLG_TX_EMPTY, &wch->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) W6692_fill_Bfifo(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) W6692B_interrupt(struct w6692_hw *card, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct w6692_ch *wch = &card->bc[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u8 stat, star = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) stat = ReadW6692B(wch, W_B_EXIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pr_debug("%s: B%d EXIR %02x\n", card->name, wch->bch.nr, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (stat & W_B_EXI_RME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) star = ReadW6692B(wch, W_B_STAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (star & (W_B_STAR_RDOV | W_B_STAR_CRCE | W_B_STAR_RMB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if ((star & W_B_STAR_RDOV) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) test_bit(FLG_ACTIVE, &wch->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pr_debug("%s: B%d RDOV proto=%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) wch->bch.nr, wch->bch.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) wch->bch.err_rdo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (test_bit(FLG_HDLC, &wch->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (star & W_B_STAR_CRCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pr_debug("%s: B%d CRC error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) card->name, wch->bch.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) wch->bch.err_crc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (star & W_B_STAR_RMB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pr_debug("%s: B%d message abort\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) card->name, wch->bch.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) wch->bch.err_inv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) W_B_CMDR_RRST | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (wch->bch.rx_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) skb_trim(wch->bch.rx_skb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) count = ReadW6692B(wch, W_B_RBCL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (W_B_FIFO_THRESH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) count = W_B_FIFO_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) W6692_empty_Bfifo(wch, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) recv_Bchannel(&wch->bch, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (stat & W_B_EXI_RMR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!(stat & W_B_EXI_RME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) star = ReadW6692B(wch, W_B_STAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (star & W_B_STAR_RDOV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pr_debug("%s: B%d RDOV proto=%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) wch->bch.nr, wch->bch.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) wch->bch.err_rdo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) W_B_CMDR_RRST | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) W6692_empty_Bfifo(wch, W_B_FIFO_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) recv_Bchannel(&wch->bch, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (stat & W_B_EXI_RDOV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* only if it is not handled yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!(star & W_B_STAR_RDOV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pr_debug("%s: B%d RDOV IRQ proto=%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) wch->bch.nr, wch->bch.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) wch->bch.err_rdo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) W_B_CMDR_RRST | W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (stat & W_B_EXI_XFR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!(stat & (W_B_EXI_RME | W_B_EXI_RMR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) star = ReadW6692B(wch, W_B_STAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pr_debug("%s: B%d star %02x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) wch->bch.nr, star);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (star & W_B_STAR_XDOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pr_warn("%s: B%d XDOW proto=%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) wch->bch.nr, wch->bch.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) wch->bch.err_xdu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) WriteW6692B(wch, W_B_CMDR, W_B_CMDR_XRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) W_B_CMDR_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* resend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (wch->bch.tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) wch->bch.tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) send_next(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (star & W_B_STAR_XDOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return; /* handle XDOW only once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (stat & W_B_EXI_XDUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pr_warn("%s: B%d XDUN proto=%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) wch->bch.nr, wch->bch.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) wch->bch.err_xdu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* resend - no XRST needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (wch->bch.tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) wch->bch.tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else if (test_bit(FLG_FILLEMPTY, &wch->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) test_and_set_bit(FLG_TX_EMPTY, &wch->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) send_next(wch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) w6692_irq(int intno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct w6692_hw *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 ista;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_lock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ista = ReadW6692(card, W_ISTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if ((ista | card->imask) == card->imask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* possible a shared IRQ reqest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) spin_unlock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) card->irqcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pr_debug("%s: ista %02x\n", card->name, ista);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ista &= ~card->imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ista & W_INT_B1_EXI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) W6692B_interrupt(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ista & W_INT_B2_EXI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) W6692B_interrupt(card, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ista & W_INT_D_RME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) handle_rxD(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ista & W_INT_D_RMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) W6692_empty_Dfifo(card, W_D_FIFO_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ista & W_INT_D_XFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) handle_txD(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ista & W_INT_D_EXI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) handle_statusD(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ista & (W_INT_XINT0 | W_INT_XINT1)) /* XINT0/1 - never */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pr_debug("%s: W6692 spurious XINT!\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* End IRQ Handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spin_unlock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dbusy_timer_handler(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct dchannel *dch = from_timer(dch, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct w6692_hw *card = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int rbch, star;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (test_bit(FLG_BUSY_TIMER, &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rbch = ReadW6692(card, W_D_RBCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) star = ReadW6692(card, W_D_STAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) card->name, rbch, star);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (star & W_D_STAR_XBZ) /* D-Channel Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) test_and_set_bit(FLG_L1_BUSY, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* discard frame; reset transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (dch->tx_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pr_info("%s: W6692 D-Channel Busy no tx_idx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Transmitter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) WriteW6692(card, W_D_CMDR, W_D_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static void initW6692(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) timer_setup(&card->dch.timer, dbusy_timer_handler, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) w6692_mode(&card->bc[0], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) w6692_mode(&card->bc[1], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) WriteW6692(card, W_D_CTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) disable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) WriteW6692(card, W_D_SAM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) WriteW6692(card, W_D_TAM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) WriteW6692(card, W_D_MODE, W_D_MODE_RACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) card->state = W_L1CMD_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ph_command(card, W_L1CMD_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ph_command(card, W_L1CMD_ECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* enable all IRQ but extern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) card->imask = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) WriteW6692(card, W_D_EXIM, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) WriteW6692B(&card->bc[0], W_B_EXIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) WriteW6692B(&card->bc[1], W_B_EXIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Reset D-chan receiver and transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Reset B-chan receiver and transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) WriteW6692B(&card->bc[0], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) WriteW6692B(&card->bc[1], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* enable peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (card->subtype == W6692_USR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* seems that USR implemented some power control features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Pin 79 is connected to the oscilator circuit so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * have to handle it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) card->pctl = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) card->xdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) WriteW6692(card, W_PCTL, card->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) WriteW6692(card, W_XDATA, card->xdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) card->pctl = W_PCTL_OE5 | W_PCTL_OE4 | W_PCTL_OE2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) W_PCTL_OE1 | W_PCTL_OE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) card->xaddr = 0x00;/* all sw off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (card->fmask & pots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) card->xdata |= 0x06; /* POWER UP/ LED OFF / ALAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (card->fmask & led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) card->xdata |= 0x04; /* LED OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if ((card->fmask & pots) || (card->fmask & led)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) WriteW6692(card, W_PCTL, card->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) WriteW6692(card, W_XADDR, card->xaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) WriteW6692(card, W_XDATA, card->xdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) val = ReadW6692(card, W_XADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pr_notice("%s: W_XADDR=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) reset_w6692(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) WriteW6692(card, W_D_CTL, W_D_CTL_SRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) WriteW6692(card, W_D_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) init_card(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) disable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (request_irq(card->irq, w6692_irq, IRQF_SHARED, card->name, card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pr_info("%s: couldn't get interrupt %d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) card->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) while (cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) initW6692(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) enable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Timeout 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pr_notice("%s: IRQ %d count %d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) card->irq, card->irqcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!card->irqcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pr_info("%s: IRQ(%d) getting no IRQs during init %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) card->name, card->irq, 3 - cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) reset_w6692(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) w6692_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct w6692_hw *card = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct mISDNhead *hh = mISDN_HEAD_P(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) switch (hh->prim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case PH_DATA_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = bchannel_senddata(bch, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret > 0) { /* direct TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) W6692_fill_Bfifo(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case PH_ACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = w6692_mode(bc, ch->protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case PH_DEACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mISDN_clear_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) w6692_mode(bc, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pr_info("%s: %s unknown prim(%x,%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) card->name, __func__, hh->prim, hh->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return mISDN_ctrl_bchannel(bch, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) open_bchannel(struct w6692_hw *card, struct channel_req *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct bchannel *bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (rq->adr.channel == 0 || rq->adr.channel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (rq->protocol == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bch = &card->bc[rq->adr.channel - 1].bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (test_and_set_bit(FLG_OPEN, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EBUSY; /* b-channel can be only open once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) bch->ch.protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) rq->ch = &bch->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) channel_ctrl(struct w6692_hw *card, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) switch (cq->op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case MISDN_CTRL_GETOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cq->op = MISDN_CTRL_L1_TIMER3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case MISDN_CTRL_L1_TIMER3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = l1_event(card->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pr_info("%s: unknown CTRL OP %x\n", card->name, cq->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) w6692_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct w6692_hw *card = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) test_and_clear_bit(FLG_OPEN, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) cancel_work_sync(&bch->workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mISDN_clear_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) w6692_mode(bc, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ch->protocol = ISDN_P_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ch->peer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = channel_bctrl(bch, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pr_info("%s: %s unknown prim(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) card->name, __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) w6692_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct dchannel *dch = container_of(dev, struct dchannel, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct mISDNhead *hh = mISDN_HEAD_P(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) switch (hh->prim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case PH_DATA_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = dchannel_senddata(dch, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ret > 0) { /* direct TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) id = hh->id; /* skb can be freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) W6692_fill_Dfifo(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case PH_ACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = l1_event(dch->l1, hh->prim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case PH_DEACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = l1_event(dch->l1, hh->prim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) w6692_l1callback(struct dchannel *dch, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pr_debug("%s: cmd(%x) state(%02x)\n", card->name, cmd, card->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case INFO3_P8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ph_command(card, W_L1CMD_AR8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case INFO3_P10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ph_command(card, W_L1CMD_AR10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case HW_RESET_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (card->state != W_L1IND_DRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ph_command(card, W_L1CMD_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ph_command(card, W_L1CMD_ECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case HW_DEACT_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) skb_queue_purge(&dch->squeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (dch->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_kfree_skb(dch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dch->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev_kfree_skb(dch->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dch->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) del_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case HW_POWERUP_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ph_command(card, W_L1CMD_ECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case PH_ACTIVATE_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) test_and_set_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case PH_DEACTIVATE_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pr_debug("%s: %s unknown command %x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) open_dchannel(struct w6692_hw *card, struct channel_req *rq, void *caller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pr_debug("%s: %s dev(%d) open from %p\n", card->name, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) card->dch.dev.id, caller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (rq->protocol != ISDN_P_TE_S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (rq->adr.channel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* E-Channel not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rq->ch = &card->dch.dev.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) rq->ch->protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (card->dch.state == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) 0, NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) w6692_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct dchannel *dch = container_of(dev, struct dchannel, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct channel_req *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pr_debug("%s: DCTRL: %x %p\n", card->name, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case OPEN_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rq = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (rq->protocol == ISDN_P_TE_S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err = open_dchannel(card, rq, __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) err = open_bchannel(card, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!try_module_get(THIS_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pr_info("%s: cannot get module\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_debug("%s: dev(%d) close from %p\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dch->dev.id, __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) err = channel_ctrl(card, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pr_debug("%s: unknown DCTRL command %x\n", card->name, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) setup_w6692(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!request_region(card->addr, 256, card->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) pr_info("%s: config port %x-%x already in use\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) card->addr, card->addr + 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) W6692Version(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) card->bc[0].addr = card->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) card->bc[1].addr = card->addr + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) val = ReadW6692(card, W_ISTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pr_notice("%s ISTA=%02x\n", card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) val = ReadW6692(card, W_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) pr_notice("%s IMASK=%02x\n", card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) val = ReadW6692(card, W_D_EXIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pr_notice("%s D_EXIR=%02x\n", card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) val = ReadW6692(card, W_D_EXIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pr_notice("%s D_EXIM=%02x\n", card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) val = ReadW6692(card, W_D_RSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pr_notice("%s D_RSTA=%02x\n", card->name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) release_card(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) disable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) w6692_mode(&card->bc[0], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) w6692_mode(&card->bc[1], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if ((card->fmask & led) || card->subtype == W6692_USR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) card->xdata |= 0x04; /* LED OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) WriteW6692(card, W_XDATA, card->xdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) l1_event(card->dch.l1, CLOSE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) mISDN_unregister_device(&card->dch.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) release_region(card->addr, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) mISDN_freebchannel(&card->bc[1].bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mISDN_freebchannel(&card->bc[0].bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mISDN_freedchannel(&card->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) write_lock_irqsave(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) list_del(&card->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) write_unlock_irqrestore(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pci_disable_device(card->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pci_set_drvdata(card->pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) setup_instance(struct w6692_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) snprintf(card->name, MISDN_MAX_IDLEN - 1, "w6692.%d", w6692_cnt + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) write_lock_irqsave(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) list_add_tail(&card->list, &Cards);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) write_unlock_irqrestore(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) card->fmask = (1 << w6692_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) _set_debug(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) spin_lock_init(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, W6692_ph_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) card->dch.dev.D.send = w6692_l2l1D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) card->dch.dev.D.ctrl = w6692_dctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) card->dch.hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) card->dch.dev.nrbchan = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) W_B_FIFO_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) card->bc[i].bch.hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) card->bc[i].bch.nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) card->bc[i].bch.ch.nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) card->bc[i].bch.ch.send = w6692_l2l1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) card->bc[i].bch.ch.ctrl = w6692_bctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) set_channelmap(i + 1, card->dch.dev.channelmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) list_add(&card->bc[i].bch.ch.list, &card->dch.dev.bchannels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) err = setup_w6692(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) goto error_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) err = mISDN_register_device(&card->dch.dev, &card->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto error_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) err = init_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) goto error_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) err = create_l1(&card->dch, w6692_l1callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) w6692_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) pr_notice("W6692 %d cards installed\n", w6692_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) error_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) mISDN_unregister_device(&card->dch.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) error_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) release_region(card->addr, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) error_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mISDN_freebchannel(&card->bc[1].bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) mISDN_freebchannel(&card->bc[0].bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) mISDN_freedchannel(&card->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) write_lock_irqsave(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) list_del(&card->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) write_unlock_irqrestore(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) w6692_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct w6692_hw *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct w6692map *m = (struct w6692map *)ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) card = kzalloc(sizeof(struct w6692_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pr_info("No kmem for w6692 card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) card->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) card->subtype = m->subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) printk(KERN_INFO "mISDN_w6692: found adapter %s at %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) m->name, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) card->addr = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) card->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) err = setup_instance(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) w6692_remove_pci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct w6692_hw *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) release_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pr_notice("%s: drvdata already removed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const struct pci_device_id w6692_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) { PCI_VENDOR_ID_DYNALINK, PCI_DEVICE_ID_DYNALINK_IS64PH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[0]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PCI_VENDOR_ID_USR, PCI_DEVICE_ID_USR_6692, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) (ulong)&w6692_map[2]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[1]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) MODULE_DEVICE_TABLE(pci, w6692_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static struct pci_driver w6692_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .name = "w6692",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .probe = w6692_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .remove = w6692_remove_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .id_table = w6692_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int __init w6692_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pr_notice("Winbond W6692 PCI driver Rev. %s\n", W6692_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) err = pci_register_driver(&w6692_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static void __exit w6692_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pci_unregister_driver(&w6692_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) module_init(w6692_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) module_exit(w6692_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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