^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NETJet mISDN driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mISDNhw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ipac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "iohelper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "netjet.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "isdnhdlc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NETJET_REV "2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum nj_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) NETJET_S_TJ300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) NETJET_S_TJ320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ENTERNOW__TJ320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct tiger_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 dmastart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 dmairq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 dmaend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 dmacur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tiger_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct tiger_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct bchannel bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tiger_hw *nj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int lastrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 rxstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 txstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct isdnhdlc_vars hsend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct isdnhdlc_vars hrecv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 *hsbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 *hrbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TX_INIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TX_IDLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TX_RUN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TX_UNDERRUN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RX_OVERRUN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LOG_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct tiger_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) char name[MISDN_MAX_IDLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum nj_types typ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 irqcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) size_t base_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void *dma_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spinlock_t lock; /* lock HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct isac_hw isac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tiger_dma send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tiger_dma recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct tiger_ch bc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 ctrlreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 dmactrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 auxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 last_is0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 irqmask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) char log[LOG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static LIST_HEAD(Cards);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static DEFINE_RWLOCK(card_lock); /* protect Cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static u32 debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int nj_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) _set_debug(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) card->isac.dch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) card->bc[0].bch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) card->bc[1].bch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) set_debug(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct tiger_hw *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = param_set_uint(val, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) read_lock(&card_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) list_for_each_entry(card, &Cards, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) _set_debug(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) read_unlock(&card_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_AUTHOR("Karsten Keil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_VERSION(NETJET_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_PARM_DESC(debug, "Netjet debug mask");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) nj_disable_hwirq(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outb(0, card->base + NJ_IRQMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) outb(0, card->base + NJ_IRQMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ReadISAC_nj(void *p, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct tiger_hw *card = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) card->auxd &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) card->auxd |= (offset >> 4) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) outb(card->auxd, card->base + NJ_AUXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) WriteISAC_nj(void *p, u8 offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct tiger_hw *card = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) card->auxd &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) card->auxd |= (offset >> 4) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outb(card->auxd, card->base + NJ_AUXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct tiger_hw *card = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) card->auxd &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outb(card->auxd, card->base + NJ_AUXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) insb(card->base + NJ_ISAC_OFF, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct tiger_hw *card = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) card->auxd &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) outb(card->auxd, card->base + NJ_AUXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) outsb(card->base + NJ_ISAC_OFF, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct tiger_hw *card = bc->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 mask = 0xff, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bc->bch.nr, fill, cnt, idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (bc->bch.nr & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) fill <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mask <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mask ^= 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) while (cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = card->send.start[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val |= fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) card->send.start[idx++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (idx >= card->send.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mode_tiger(struct tiger_ch *bc, u32 protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct tiger_hw *card = bc->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bc->bch.nr, bc->bch.state, protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) switch (protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case ISDN_P_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (bc->bch.state == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) fill_mem(bc, 0, card->send.size, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bc->bch.state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* only stop dma and interrupts if both channels NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if ((card->bc[0].bch.state == ISDN_P_NONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (card->bc[1].bch.state == ISDN_P_NONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) card->dmactrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) outb(card->dmactrl, card->base + NJ_DMACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) outb(0, card->base + NJ_IRQMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bc->txstate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bc->rxstate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bc->lastrx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case ISDN_P_B_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bc->bch.state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bc->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bc->free = card->send.size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) bc->rxstate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bc->txstate = TX_INIT | TX_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bc->lastrx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!card->dmactrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) card->dmactrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) outb(card->dmactrl, card->base + NJ_DMACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) outb(0x0f, card->base + NJ_IRQMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case ISDN_P_B_HDLC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bc->bch.state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bc->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bc->free = card->send.size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bc->rxstate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bc->txstate = TX_INIT | TX_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) isdnhdlc_rcv_init(&bc->hrecv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) isdnhdlc_out_init(&bc->hsend, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bc->lastrx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!card->dmactrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) card->dmactrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) outb(card->dmactrl, card->base + NJ_DMACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) outb(0x0f, card->base + NJ_IRQMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pr_info("%s: %s protocol %x not handled\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __func__, protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENOPROTOOPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) card->name, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) inb(card->base + NJ_DMACTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) inb(card->base + NJ_IRQMASK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) inb(card->base + NJ_IRQSTAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) card->send.idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) card->recv.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) nj_reset(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) outb(0xff, card->base + NJ_CTRL); /* Reset On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* now edge triggered for TJ320 GE 13/07/00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* see comment in IRQ function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (card->typ == NETJET_S_TJ320) /* TJ320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) card->ctrlreg = 0x40; /* Reset Off and status read clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) card->ctrlreg = 0x00; /* Reset Off and status read clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) outb(card->ctrlreg, card->base + NJ_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* configure AUX pins (all output except ISAC IRQ pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) card->auxd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) card->dmactrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) outb(card->auxd, card->base + NJ_AUXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) inittiger(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) card->dma_p = dma_alloc_coherent(&card->pdev->dev, NJ_DMA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &card->dma, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!card->dma_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pr_info("%s: No DMA memory\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if ((u64)card->dma > 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pr_info("%s: DMA outside 32 bit\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!card->bc[i].hsbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_info("%s: no B%d send buffer\n", card->name, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!card->bc[i].hrbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) memset(card->dma_p, 0xff, NJ_DMA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) card->send.start = card->dma_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) card->send.dmastart = (u32)card->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) card->send.dmaend = card->send.dmastart +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) (4 * (NJ_DMA_TXSIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) card->send.dmairq = card->send.dmastart +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (4 * ((NJ_DMA_TXSIZE / 2) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) card->send.size = NJ_DMA_TXSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) " size %zu u32\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) card->send.dmastart, card->send.dmairq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) card->send.dmaend, card->send.start, card->send.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) card->recv.dmaend = card->recv.dmastart +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (4 * (NJ_DMA_RXSIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) card->recv.dmairq = card->recv.dmastart +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (4 * ((NJ_DMA_RXSIZE / 2) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) card->recv.size = NJ_DMA_RXSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) " size %zu u32\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) card->recv.dmastart, card->recv.dmairq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) card->recv.dmaend, card->recv.start, card->recv.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) read_dma(struct tiger_ch *bc, u32 idx, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct tiger_hw *card = bc->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int i, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 *p, *pn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (bc->lastrx == idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bc->rxstate |= RX_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pr_info("%s: B%1d overrun at idx %d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bc->bch.nr, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bc->lastrx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (test_bit(FLG_RX_OFF, &bc->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bc->bch.dropcnt += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) stat = bchannel_get_rxbuf(&bc->bch, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* only transparent use the count here, HDLC overun is detected later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (stat == -ENOMEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pr_warn("%s.B%d: No memory for %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) card->name, bc->bch.nr, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) p = skb_put(bc->bch.rx_skb, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) p = bc->hrbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (i = 0; i < cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val = card->recv.start[idx++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (bc->bch.nr & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (idx >= card->recv.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) p[i] = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) recv_Bchannel(&bc->bch, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pn = bc->hrbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) while (cnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bc->bch.rx_skb->data, bc->bch.maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (stat > 0) { /* valid frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) p = skb_put(bc->bch.rx_skb, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (debug & DEBUG_HW_BFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) snprintf(card->log, LOG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "B%1d-recv %s %d ", bc->bch.nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) card->name, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) print_hex_dump_bytes(card->log,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DUMP_PREFIX_OFFSET, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) recv_Bchannel(&bc->bch, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (stat < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pr_warn("%s.B%d: No memory for %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) card->name, bc->bch.nr, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) } else if (stat == -HDLC_CRC_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_info("%s: B%1d receive frame CRC error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) card->name, bc->bch.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else if (stat == -HDLC_FRAMING_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pr_info("%s: B%1d receive framing error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) card->name, bc->bch.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else if (stat == -HDLC_LENGTH_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pr_info("%s: B%1d receive frame too long (> %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) card->name, bc->bch.nr, bc->bch.maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pn += i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cnt -= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) recv_tiger(struct tiger_hw *card, u8 irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int cnt = card->recv.size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Note receive is via the WRITE DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) card->last_is0 &= ~NJ_IRQM0_WR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (irq_stat & NJ_IRQM0_WR_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) idx = cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) idx = card->recv.size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) read_dma(&card->bc[0], idx, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) read_dma(&card->bc[1], idx, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* sync with current DMA address at start or after exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) resync(struct tiger_ch *bc, struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (bc->free > card->send.size / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bc->free = card->send.size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* currently we simple sync to the next complete free area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * this hast the advantage that we have always maximum time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * handle TX irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (card->send.idx < ((card->send.size / 2) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bc->idx = (card->recv.size / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bc->idx = card->recv.size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bc->txstate = TX_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int bc_next_frame(struct tiger_ch *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) fill_hdlc_flag(struct tiger_ch *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tiger_hw *card = bc->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 m, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (bc->free == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __func__, bc->bch.nr, bc->free, bc->txstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bc->idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) resync(bc, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bc->hsbuf, bc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bc->bch.nr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) bc->free -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) p = bc->hsbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (bc->idx >= card->send.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bc->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) v = card->send.start[bc->idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) v &= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) card->send.start[bc->idx++] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (debug & DEBUG_HW_BFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bc->bch.nr, card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fill_dma(struct tiger_ch *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct tiger_hw *card = bc->bch.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int count, i, fillempty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 m, v, n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (bc->free == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!bc->bch.tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!test_bit(FLG_TX_EMPTY, &bc->bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fillempty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) count = card->send.size >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) p = bc->bch.fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) count = bc->bch.tx_skb->len - bc->bch.tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) card->name, __func__, bc->bch.nr, count, bc->free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bc->bch.tx_idx, bc->bch.tx_skb->len, bc->txstate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bc->idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) p = bc->bch.tx_skb->data + bc->bch.tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) resync(bc, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (test_bit(FLG_HDLC, &bc->bch.Flags) && !fillempty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) count = isdnhdlc_encode(&bc->hsend, p, count, &i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bc->hsbuf, bc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bc->bch.nr, i, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bc->bch.tx_idx += i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bc->free -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) p = bc->hsbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (count > bc->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) count = bc->free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!fillempty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bc->bch.tx_idx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bc->free -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (fillempty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) n = p[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!(bc->bch.nr & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) n <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (bc->idx >= card->send.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bc->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) v = card->send.start[bc->idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) v &= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) v |= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) card->send.start[bc->idx++] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (bc->idx >= card->send.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bc->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) v = card->send.start[bc->idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) v &= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) n = p[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) v |= (bc->bch.nr & 1) ? n : n << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) card->send.start[bc->idx++] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (debug & DEBUG_HW_BFIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bc->bch.nr, card->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (bc->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bc_next_frame(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bc_next_frame(struct tiger_ch *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fill_dma(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_kfree_skb(bc->bch.tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (get_next_bframe(&bc->bch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fill_dma(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) test_and_clear_bit(FLG_TX_EMPTY, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } else if (test_bit(FLG_TX_EMPTY, &bc->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fill_dma(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else if (test_bit(FLG_FILLEMPTY, &bc->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) test_and_set_bit(FLG_TX_EMPTY, &bc->bch.Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bc->free += card->send.size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (bc->free >= card->send.size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pr_info("%s: B%1d TX underrun state %x\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bc->bch.nr, bc->txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) bc->txstate |= TX_UNDERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bc->free = card->send.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = bc_next_frame(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fill_hdlc_flag(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bc->bch.nr, bc->free, bc->idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fill_mem(bc, bc->idx, bc->free, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (bc->free == card->send.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) bc->txstate |= TX_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) send_tiger(struct tiger_hw *card, u8 irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Note send is via the READ DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pr_info("%s: tiger warn write double dma %x/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) card->name, irq_stat, card->last_is0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) card->last_is0 &= ~NJ_IRQM0_RD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) send_tiger_bc(card, &card->bc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) nj_irq(int intno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct tiger_hw *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 val, s1val, s0val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) spin_lock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) s0val = inb(card->base | NJ_IRQSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) s1val = inb(card->base | NJ_IRQSTAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* shared IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_unlock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) card->irqcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!(s1val & NJ_ISACIRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val = ReadISAC_nj(card, ISAC_ISTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mISDNisac_irq(&card->isac, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (s0val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* write to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) outb(s0val, card->base | NJ_IRQSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) s1val = s0val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* set bits in sval to indicate which page is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (card->recv.dmacur < card->recv.dmairq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) s0val = 0x08; /* the 2nd write area is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) s0val = 0x04; /* the 1st write area is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (card->send.dmacur < card->send.dmairq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) s0val |= 0x02; /* the 2nd read area is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) s0val |= 0x01; /* the 1st read area is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) s1val, s0val, card->last_is0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) card->recv.idx, card->send.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* test if we have a DMA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (s0val != card->last_is0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if ((s0val & NJ_IRQM0_RD_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (card->last_is0 & NJ_IRQM0_RD_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* got a write dma int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) send_tiger(card, s0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if ((s0val & NJ_IRQM0_WR_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (card->last_is0 & NJ_IRQM0_WR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* got a read dma int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) recv_tiger(card, s0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) spin_unlock(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct tiger_hw *card = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct mISDNhead *hh = mISDN_HEAD_P(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) switch (hh->prim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case PH_DATA_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = bchannel_senddata(bch, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret > 0) { /* direct TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fill_dma(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case PH_ACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = mode_tiger(bc, ch->protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case PH_DEACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mISDN_clear_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mode_tiger(bc, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return mISDN_ctrl_bchannel(&bc->bch, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct tiger_hw *card = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) test_and_clear_bit(FLG_OPEN, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cancel_work_sync(&bch->workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mISDN_clear_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mode_tiger(bc, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ch->protocol = ISDN_P_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ch->peer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = channel_bctrl(bc, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) switch (cq->op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case MISDN_CTRL_GETOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case MISDN_CTRL_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (cq->channel < 0 || cq->channel > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case MISDN_CTRL_L1_TIMER3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) open_bchannel(struct tiger_hw *card, struct channel_req *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct bchannel *bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (rq->adr.channel == 0 || rq->adr.channel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (rq->protocol == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) bch = &card->bc[rq->adr.channel - 1].bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (test_and_set_bit(FLG_OPEN, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EBUSY; /* b-channel can be only open once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) bch->ch.protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) rq->ch = &bch->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * device control function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct dchannel *dch = container_of(dev, struct dchannel, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct tiger_hw *card = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct channel_req *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case OPEN_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) rq = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (rq->protocol == ISDN_P_TE_S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) err = card->isac.open(&card->isac, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) err = open_bchannel(card, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!try_module_get(THIS_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pr_info("%s: cannot get module\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) err = channel_ctrl(card, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pr_debug("%s: %s unknown command %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) card->name, __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) nj_init_card(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) nj_disable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) card->irq = card->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pr_info("%s: couldn't get interrupt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) card->name, card->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) card->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) nj_reset(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = card->isac.init(&card->isac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = inittiger(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mode_tiger(&card->bc[0], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mode_tiger(&card->bc[1], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) nj_release(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (card->base_s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) spin_lock_irqsave(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) nj_disable_hwirq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mode_tiger(&card->bc[0], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mode_tiger(&card->bc[1], ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) spin_unlock_irqrestore(&card->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) card->isac.release(&card->isac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) release_region(card->base, card->base_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) card->base_s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (card->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (card->isac.dch.dev.dev.class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mISDN_unregister_device(&card->isac.dch.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mISDN_freebchannel(&card->bc[i].bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) kfree(card->bc[i].hsbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) kfree(card->bc[i].hrbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (card->dma_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dma_free_coherent(&card->pdev->dev, NJ_DMA_SIZE, card->dma_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) card->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) write_lock_irqsave(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) list_del(&card->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) write_unlock_irqrestore(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pci_clear_master(card->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pci_disable_device(card->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pci_set_drvdata(card->pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) nj_setup(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) card->base = pci_resource_start(card->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) card->base_s = pci_resource_len(card->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!request_region(card->base, card->base_s, card->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pr_info("%s: NETjet config port %#x-%#x already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) card->name, card->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) (u32)(card->base + card->base_s - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) card->base_s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ASSIGN_FUNC(nj, ISAC, card->isac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) setup_instance(struct tiger_hw *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) write_lock_irqsave(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) list_add_tail(&card->list, &Cards);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) write_unlock_irqrestore(&card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) _set_debug(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) card->isac.name = card->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) spin_lock_init(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) card->isac.hwlock = &card->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) mISDNisac_init(&card->isac, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) card->isac.dch.dev.D.ctrl = nj_dctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) card->bc[i].bch.nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) set_channelmap(i + 1, card->isac.dch.dev.channelmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) NJ_DMA_RXSIZE >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) card->bc[i].bch.hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) card->bc[i].bch.ch.send = nj_l2l1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) card->bc[i].bch.ch.ctrl = nj_bctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) card->bc[i].bch.ch.nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) list_add(&card->bc[i].bch.ch.list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &card->isac.dch.dev.bchannels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) card->bc[i].bch.hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) err = nj_setup(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) err = nj_init_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) nj_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pr_notice("Netjet %d cards installed\n", nj_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) nj_release(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct tiger_hw *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (pdev->subsystem_vendor == 0x8086 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pdev->subsystem_device == 0x0003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pr_notice("Netjet: Digium X100P/X101P not handled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (pdev->subsystem_vendor == 0x55 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pdev->subsystem_device == 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pr_notice("Netjet: Enter!Now not handled yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (pdev->subsystem_vendor == 0xb100 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pdev->subsystem_device == 0x0003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pr_notice("Netjet: Digium TDM400P not handled yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) card = kzalloc(sizeof(struct tiger_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pr_info("No kmem for Netjet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) card->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* the TJ300 and TJ320 must be detected, the IRQ handling is different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * unfortunately the chips use the same device ID, but the TJ320 has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * the bit20 in status PCI cfg register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pci_read_config_dword(pdev, 0x04, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (cfg & 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) card->typ = NETJET_S_TJ320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) card->typ = NETJET_S_TJ300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) card->base = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) err = setup_instance(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void nj_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct tiger_hw *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) nj_release(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pr_info("%s drvdata already removed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* We cannot select cards with PCI_SUB... IDs, since here are cards with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * SUB IDs set to PCI_ANY_ID, so we need to match all and reject
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * known other cards which not work with this driver - see probe function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct pci_device_id nj_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) MODULE_DEVICE_TABLE(pci, nj_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static struct pci_driver nj_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .name = "netjet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .probe = nj_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .remove = nj_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .id_table = nj_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int __init nj_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) err = pci_register_driver(&nj_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void __exit nj_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pci_unregister_driver(&nj_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) module_init(nj_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) module_exit(nj_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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