Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * isar.h   ISAR (Siemens PSB 7110) specific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author Karsten Keil (keil@isdn4linux.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "iohelper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct isar_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct isar_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct bchannel		bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct isar_hw		*is;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	struct timer_list	ftimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8			nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u8			dpath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u8			mml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8			state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u8			cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u8			mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8			newcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u8			newmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u8			try_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u8			conmsg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct isar_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct	isar_ch	ch[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void		*hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	spinlock_t	*hwlock;	/* lock HW access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct module	*owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	read_reg_func	*read_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	write_reg_func	*write_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	fifo_func	*read_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	fifo_func	*write_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int		(*ctrl)(void *, u32, u_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void		(*release)(struct isar_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int		(*init)(struct isar_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int		(*open)(struct isar_hw *, struct channel_req *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int		(*firmware)(struct isar_hw *, const u8 *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long	Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int		version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u8		bstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8		iis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8		cmsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8		clsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u8		buf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8		log[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ISAR_IRQMSK	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ISAR_IRQSTA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ISAR_IRQBIT	0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ISAR_CTRL_H	0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ISAR_CTRL_L	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ISAR_IIS	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ISAR_IIA	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ISAR_HIS	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ISAR_HIA	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ISAR_MBOX	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ISAR_WADR	0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ISAR_RADR	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ISAR_HIS_VNR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ISAR_HIS_DKEY		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ISAR_HIS_FIRM		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ISAR_HIS_STDSP		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ISAR_HIS_DIAG		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ISAR_HIS_P0CFG		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ISAR_HIS_P12CFG		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ISAR_HIS_SARTCFG	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ISAR_HIS_PUMPCFG	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ISAR_HIS_PUMPCTRL	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ISAR_HIS_IOM2CFG	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define ISAR_HIS_IOM2REQ	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ISAR_HIS_IOM2CTRL	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ISAR_HIS_BSTREQ		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define ISAR_HIS_PSTREQ		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ISAR_HIS_SDATA		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ISAR_HIS_DPS1		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ISAR_HIS_DPS2		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SET_DPS(x)		((x << 6) & 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ISAR_IIS_MSCMSD		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ISAR_IIS_VNR		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ISAR_IIS_DKEY		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ISAR_IIS_FIRM		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ISAR_IIS_STDSP		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ISAR_IIS_DIAG		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ISAR_IIS_GSTEV		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ISAR_IIS_BSTEV		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ISAR_IIS_BSTRSP		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ISAR_IIS_PSTRSP		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ISAR_IIS_PSTEV		0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ISAR_IIS_IOM2RSP	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ISAR_IIS_RDATA		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ISAR_IIS_INVMSG		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ISAR_CTRL_SWVER	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ISAR_CTRL_STST	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ISAR_MSG_HWVER	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ISAR_DP1_USE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ISAR_DP2_USE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ISAR_RATE_REQ	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMOD_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMOD_FAX	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMOD_DATAMODEM	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMOD_HALFDUPLEX	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMOD_V110	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMOD_DTMF	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMOD_DTMF_TRANS	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMOD_BYPASS	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCTRL_ORIG	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PV32P2_V23R	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PV32P2_V22A	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PV32P2_V22B	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PV32P2_V22C	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PV32P2_V21	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PV32P2_BEL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* LSB MSB in ISAR doc wrong !!! Arghhh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PV32P3_AMOD	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PV32P3_V32B	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PV32P3_V23B	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PV32P4_48	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PV32P5_48	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PV32P4_UT48	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PV32P5_UT48	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PV32P4_96	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PV32P5_96	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PV32P4_UT96	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PV32P5_UT96	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PV32P4_B96	0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PV32P5_B96	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PV32P4_UTB96	0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PV32P5_UTB96	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PV32P4_120	0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PV32P5_120	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PV32P4_UT120	0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PV32P5_UT120	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PV32P4_144	0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PV32P5_144	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PV32P4_UT144	0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PV32P5_UT144	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PV32P6_CTN	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PV32P6_ATN	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PFAXP2_CTN	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PFAXP2_ATN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PSEV_10MS_TIMER	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PSEV_CON_ON	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PSEV_CON_OFF	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PSEV_V24_OFF	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PSEV_CTS_ON	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PSEV_CTS_OFF	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PSEV_DCD_ON	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PSEV_DCD_OFF	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PSEV_DSR_ON	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PSEV_DSR_OFF	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PSEV_REM_RET	0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PSEV_REM_REN	0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PSEV_GSTN_CLR	0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PSEV_RSP_READY	0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PSEV_LINE_TX_H	0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PSEV_LINE_TX_B	0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PSEV_LINE_RX_H	0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PSEV_LINE_RX_B	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PSEV_RSP_CONN	0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PSEV_RSP_DISC	0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PSEV_RSP_FCERR	0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PSEV_RSP_SILDET	0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PSEV_RSP_SILOFF	0xab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PSEV_FLAGS_DET	0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCTRL_CMD_TDTMF	0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCTRL_CMD_FTH	0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCTRL_CMD_FRH	0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCTRL_CMD_FTM	0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCTRL_CMD_FRM	0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCTRL_CMD_SILON	0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCTRL_CMD_CONT	0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PCTRL_CMD_ESC	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PCTRL_CMD_SILOFF 0xab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PCTRL_CMD_HALT	0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCTRL_LOC_RET	0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PCTRL_LOC_REN	0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SMODE_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SMODE_V14	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SMODE_HDLC	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SMODE_BINARY	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SMODE_FSK_V14	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SCTRL_HDMC_BOTH	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SCTRL_HDMC_DTX	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SCTRL_HDMC_DRX	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define S_P1_OVSP	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define S_P1_SNP	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define S_P1_EOP	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define S_P1_EDP	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define S_P1_NSB	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define S_P1_CHS_8	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define S_P1_CHS_7	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define S_P1_CHS_6	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define S_P1_CHS_5	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define S_P2_BFT_DEF	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IOM_CTRL_ENA	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IOM_CTRL_NOPCM	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IOM_CTRL_ALAW	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IOM_CTRL_ULAW	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IOM_CTRL_RCV	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IOM_P1_TXD	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HDLC_FED	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HDLC_FSD	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HDLC_FST	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDLC_ERROR	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HDLC_ERR_FAD	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HDLC_ERR_RER	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HDLC_ERR_CER	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SART_NMD	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BSTAT_RDM0	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define BSTAT_RDM1	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BSTAT_RDM2	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BSTAT_RDM3	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BSTEV_TBO	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BSTEV_RBO	0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* FAX State Machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STFAX_NULL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STFAX_READY	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STFAX_LINE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define STFAX_CONT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STFAX_ACTIV	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define STFAX_ESCAPE	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STFAX_SILDET	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extern u32 mISDNisar_init(struct isar_hw *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) extern void mISDNisar_irq(struct isar_hw *);