Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * ipac.h	Defines for the Infineon (former Siemens) ISDN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *		chip series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author       Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "iohelper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) struct isac_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	struct dchannel		dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u32			type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	u32			off;		/* offset to isac regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	char			*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	spinlock_t		*hwlock;	/* lock HW access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	read_reg_func		*read_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	write_reg_func		*write_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	fifo_func		*read_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	fifo_func		*write_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int			(*monitor)(void *, u32, u8 *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	void			(*release)(struct isac_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	int			(*init)(struct isac_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	int			(*ctrl)(struct isac_hw *, u32, u_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int			(*open)(struct isac_hw *, struct channel_req *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8			*mon_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u8			*mon_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int			mon_txp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	int			mon_txc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int			mon_rxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct arcofi_msg	*arcofi_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct timer_list	arcofitimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	wait_queue_head_t	arcofi_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u8			arcofi_bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u8			arcofi_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8			mocr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8			adf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8			state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct ipac_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct hscx_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct bchannel		bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct ipac_hw		*ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8			fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8			off;	/* offset to ICA or ICB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8			slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	char			log[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct ipac_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct isac_hw		isac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct hscx_hw		hscx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	char			*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void			*hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	spinlock_t		*hwlock;	/* lock HW access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct module		*owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32			type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	read_reg_func		*read_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	write_reg_func		*write_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	fifo_func		*read_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	fifo_func		*write_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	void			(*release)(struct ipac_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int			(*init)(struct ipac_hw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int			(*ctrl)(struct ipac_hw *, u32, u_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8			conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IPAC_TYPE_ISAC		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IPAC_TYPE_IPAC		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IPAC_TYPE_ISACX		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IPAC_TYPE_IPACX		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IPAC_TYPE_HSCX		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ISAC_USE_ARCOFI		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* Monitor functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MONITOR_RX_0		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MONITOR_RX_1		0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MONITOR_TX_0		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MONITOR_TX_1		0x2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* All registers original Siemens Spec  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* IPAC/ISAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ISAC_ISTA		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ISAC_MASK		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ISAC_CMDR		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ISAC_STAR		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ISAC_MODE		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ISAC_TIMR		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ISAC_EXIR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ISAC_RBCL		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ISAC_RSTA		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ISAC_RBCH		0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ISAC_SPCR		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ISAC_CIR0		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ISAC_CIX0		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ISAC_MOR0		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ISAC_MOX0		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ISAC_CIR1		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ISAC_CIX1		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ISAC_MOR1		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ISAC_MOX1		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ISAC_STCR		0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ISAC_ADF1		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ISAC_ADF2		0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ISAC_MOCR		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ISAC_MOSR		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ISAC_SQRR		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ISAC_SQXR		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ISAC_RBCH_XAC		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IPAC_D_TIN2		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* IPAC/HSCX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IPAC_ISTAB		0x20	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IPAC_MASKB		0x20	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IPAC_STARB		0x21	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IPAC_CMDRB		0x21	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IPAC_MODEB		0x22	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IPAC_EXIRB		0x24	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IPAC_RBCLB		0x25	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IPAC_RAH1		0x26	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IPAC_RAH2		0x27	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPAC_RSTAB		0x27	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IPAC_RAL1		0x28	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IPAC_RAL2		0x29	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IPAC_RHCRB		0x29	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPAC_XBCL		0x2A	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IPAC_CCR2		0x2C	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IPAC_RBCHB		0x2D	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IPAC_XBCH		0x2D	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HSCX_VSTR		0x2E	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IPAC_RLCR		0x2E	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IPAC_CCR1		0x2F	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IPAC_TSAX		0x30	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IPAC_TSAR		0x31	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IPAC_XCCR		0x32	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IPAC_RCCR		0x33	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* IPAC_ISTAB/IPAC_MASKB bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IPAC_B_XPR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IPAC_B_RPF		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IPAC_B_RME		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IPAC_B_ON		0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* IPAC_EXIRB bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IPAC_B_RFS		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IPAC_B_RFO		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IPAC_B_XDU		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IPAC_B_XMR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* IPAC special registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IPAC_CONF		0xC0	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IPAC_ISTA		0xC1	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IPAC_MASK		0xC1	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IPAC_ID			0xC2	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IPAC_ACFG		0xC3	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IPAC_AOE		0xC4	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IPAC_ARX		0xC5	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IPAC_ATX		0xC5	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IPAC_PITA1		0xC6	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IPAC_PITA2		0xC7	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IPAC_POTA1		0xC8	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IPAC_POTA2		0xC9	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IPAC_PCFG		0xCA	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IPAC_SCFG		0xCB	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IPAC_TIMR2		0xCC	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* IPAC_ISTA/_MASK bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IPAC__EXB		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IPAC__ICB		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IPAC__EXA		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IPAC__ICA		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IPAC__EXD		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IPAC__ICD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IPAC__INT0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IPAC__INT1		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IPAC__ON		0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* HSCX ISTA/MASK bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HSCX__EXB		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HSCX__EXA		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HSCX__ICA		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* ISAC/ISACX/IPAC/IPACX L1 commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ISAC_CMD_TIM		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ISAC_CMD_RS		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ISAC_CMD_SCZ		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ISAC_CMD_SSZ		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ISAC_CMD_AR8		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ISAC_CMD_AR10		0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ISAC_CMD_ARL		0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ISAC_CMD_DUI		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* ISAC/ISACX/IPAC/IPACX L1 indications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ISAC_IND_DR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ISAC_IND_RS		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ISAC_IND_SD		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ISAC_IND_DIS		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ISAC_IND_RSY		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ISAC_IND_DR6		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ISAC_IND_EI		0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ISAC_IND_PU		0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ISAC_IND_ARD		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ISAC_IND_TI		0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ISAC_IND_ATI		0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ISAC_IND_AI8		0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ISAC_IND_AI10		0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ISAC_IND_DID		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* the new ISACX / IPACX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* D-channel registers   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ISACX_RFIFOD		0x00	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ISACX_XFIFOD		0x00	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ISACX_ISTAD		0x20	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ISACX_MASKD		0x20	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ISACX_STARD		0x21	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ISACX_CMDRD		0x21	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ISACX_MODED		0x22	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ISACX_EXMD1		0x23	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ISACX_TIMR1		0x24	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ISACX_SAP1		0x25	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ISACX_SAP2		0x26	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ISACX_RBCLD		0x26	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ISACX_RBCHD		0x27	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ISACX_TEI1		0x27	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ISACX_TEI2		0x28	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ISACX_RSTAD		0x28	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ISACX_TMD		0x29	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ISACX_CIR0		0x2E	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ISACX_CIX0		0x2E	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ISACX_CIR1		0x2F	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ISACX_CIX1		0x2F	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Transceiver registers  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ISACX_TR_CONF0		0x30	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ISACX_TR_CONF1		0x31	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ISACX_TR_CONF2		0x32	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ISACX_TR_STA		0x33	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ISACX_TR_CMD		0x34	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ISACX_SQRR1		0x35	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ISACX_SQXR1		0x35	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ISACX_SQRR2		0x36	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ISACX_SQXR2		0x36	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ISACX_SQRR3		0x37	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ISACX_SQXR3		0x37	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ISACX_ISTATR		0x38	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ISACX_MASKTR		0x39	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ISACX_TR_MODE		0x3A	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ISACX_ACFG1		0x3C	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ISACX_ACFG2		0x3D	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ISACX_AOE		0x3E	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ISACX_ARX		0x3F	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ISACX_ATX		0x3F	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* IOM: Timeslot, DPS, CDA  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ISACX_CDA10		0x40	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ISACX_CDA11		0x41	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ISACX_CDA20		0x42	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ISACX_CDA21		0x43	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ISACX_CDA_TSDP10	0x44	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ISACX_CDA_TSDP11	0x45	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ISACX_CDA_TSDP20	0x46	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ISACX_CDA_TSDP21	0x47	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ISACX_BCHA_TSDP_BC1	0x48	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ISACX_BCHA_TSDP_BC2	0x49	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ISACX_BCHB_TSDP_BC1	0x4A	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ISACX_BCHB_TSDP_BC2	0x4B	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ISACX_TR_TSDP_BC1	0x4C	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ISACX_TR_TSDP_BC2	0x4D	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ISACX_CDA1_CR		0x4E	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ISACX_CDA2_CR		0x4F	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* IOM: Contol, Sync transfer, Monitor    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ISACX_TR_CR		0x50	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ISACX_TRC_CR		0x50	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ISACX_BCHA_CR		0x51	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ISACX_BCHB_CR		0x52	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ISACX_DCI_CR		0x53	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ISACX_DCIC_CR		0x53	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ISACX_MON_CR		0x54	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ISACX_SDS1_CR		0x55	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ISACX_SDS2_CR		0x56	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ISACX_IOM_CR		0x57	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ISACX_STI		0x58	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ISACX_ASTI		0x58	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ISACX_MSTI		0x59	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ISACX_SDS_CONF		0x5A	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ISACX_MCDA		0x5B	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ISACX_MOR		0x5C	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ISACX_MOX		0x5C	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ISACX_MOSR		0x5D	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ISACX_MOCR		0x5E	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ISACX_MSTA		0x5F	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ISACX_MCONF		0x5F	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Interrupt and general registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ISACX_ISTA		0x60	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ISACX_MASK		0x60	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ISACX_AUXI		0x61	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ISACX_AUXM		0x61	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ISACX_MODE1		0x62	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ISACX_MODE2		0x63	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ISACX_ID		0x64	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ISACX_SRES		0x64	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ISACX_TIMR2		0x65	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* ISACX/IPACX _ISTAD (R) and _MASKD (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ISACX_D_XDU		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define ISACX_D_XMR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ISACX_D_XPR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ISACX_D_RFO		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ISACX_D_RPF		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ISACX_D_RME		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ISACX/IPACX _ISTA (R) and _MASK (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ISACX__ICD		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ISACX__MOS		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ISACX__TRAN		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ISACX__AUX		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ISACX__CIC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ISACX__ST		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IPACX__ON		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IPACX__ICB		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IPACX__ICA		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* ISACX/IPACX _CMDRD (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ISACX_CMDRD_XRES	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ISACX_CMDRD_XME		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ISACX_CMDRD_XTF		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ISACX_CMDRD_STI		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ISACX_CMDRD_RRES	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ISACX_CMDRD_RMC		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* ISACX/IPACX _RSTAD (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ISACX_RSTAD_TA		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ISACX_RSTAD_CR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ISACX_RSTAD_SA0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ISACX_RSTAD_SA1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ISACX_RSTAD_RAB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ISACX_RSTAD_CRC		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ISACX_RSTAD_RDO		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ISACX_RSTAD_VFR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* ISACX/IPACX _CIR0 (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ISACX_CIR0_BAS		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ISACX_CIR0_SG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ISACX_CIR0_CIC1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ISACX_CIR0_CIC0		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* B-channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IPACX_OFF_ICA		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IPACX_OFF_ICB		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* ICA: IPACX_OFF_ICA + Reg ICB: IPACX_OFF_ICB + Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IPACX_ISTAB		0x00    /* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IPACX_MASKB		0x00	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IPACX_STARB		0x01	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IPACX_CMDRB		0x01	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IPACX_MODEB		0x02	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IPACX_EXMB		0x03	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IPACX_RAH1		0x05	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IPACX_RAH2		0x06	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IPACX_RBCLB		0x06	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IPACX_RBCHB		0x07	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IPACX_RAL1		0x07	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IPACX_RAL2		0x08	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IPACX_RSTAB		0x08	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IPACX_TMB		0x09	/* R/W	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IPACX_RFIFOB		0x0A	/* RD	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IPACX_XFIFOB		0x0A	/* WR	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* IPACX_ISTAB / IPACX_MASKB bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IPACX_B_XDU		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IPACX_B_XPR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IPACX_B_RFO		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IPACX_B_RPF		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IPACX_B_RME		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IPACX_B_ON		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) extern int mISDNisac_init(struct isac_hw *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) extern irqreturn_t mISDNisac_irq(struct isac_hw *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) extern u32 mISDNipac_init(struct ipac_hw *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) extern irqreturn_t mISDNipac_irq(struct ipac_hw *, int);