^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * hfcpci.c low level driver for CCD's hfc-pci based cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author Werner Cornelius (werner@isdn4linux.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on existing driver for CCD hfc ISA cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * type approval valid for HFC-S PCI A based card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright 2008 by Karsten Keil <kkeil@novell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Module options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * debug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NOTE: only one poll value must be given for all cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * See hfc_pci.h for debug flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * poll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * NOTE: only one poll value must be given for all cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Give the number of samples for each fifo process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * By default 128 is used. Decrease to reduce delay, increase to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * reduce cpu load. If unsure, don't mess with it!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * A value of 128 will use controller's interrupt. Other values will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * use kernel timer, because the controller will not allow lower values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * than 128.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Also note that the value depends on the kernel timer frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * If the kernel uses 100 Hz, steps of 80 samples are possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * If the kernel uses 300 Hz, steps of about 26 samples are possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mISDNhw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "hfc_pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *hfcpci_revision = "2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int HFC_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static uint debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static uint poll, tics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct timer_list hfc_tl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static unsigned long hfc_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_AUTHOR("Karsten Keil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param(debug, uint, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(poll, uint, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) HFC_CCD_2BD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) HFC_CCD_B000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) HFC_CCD_B006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) HFC_CCD_B007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) HFC_CCD_B008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) HFC_CCD_B009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) HFC_CCD_B00A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) HFC_CCD_B00B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) HFC_CCD_B00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) HFC_CCD_B100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) HFC_CCD_B700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) HFC_CCD_B701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) HFC_ASUS_0675,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) HFC_BERKOM_A1T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) HFC_BERKOM_TCONCEPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) HFC_ANIGMA_MC145575,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HFC_ZOLTRIX_2BD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) HFC_DIGI_DF_M_IOM2_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HFC_DIGI_DF_M_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HFC_DIGI_DF_M_IOM2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HFC_DIGI_DF_M_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HFC_ABOCOM_2BD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) HFC_SITECOM_DC105V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct hfcPCI_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned char cirm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char ctmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned char clkdel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned char mst_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned char int_m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned char int_m2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned char sctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned char sctrl_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned char sctrl_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned char trm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned char fifo_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned char bswapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned char protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int nt_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned char __iomem *pci_io; /* start of PCI IO memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dma_addr_t dmahandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void *fifos; /* FIFO memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int last_bfifo_cnt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* marker saving last b-fifo frame count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HFC_CFG_MASTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HFC_CFG_SLAVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HFC_CFG_PCM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HFC_CFG_2HFC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HFC_CFG_SLAVEHFC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HFC_CFG_NEG_F0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HFC_CFG_SW_DD_DU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FLG_HFC_TIMER_T1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FLG_HFC_TIMER_T3 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct hfc_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u_char subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u_char chanlimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u_char initdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u_long cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u_int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u_int irqcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct hfcPCI_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spinlock_t lock; /* card lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dchannel dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct bchannel bch[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Interface functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enable_hwirq(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) disable_hwirq(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * free hardware resources used by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) release_io_hfcpci(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* disable memory mapped ports + busmaster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) del_timer(&hc->hw.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hc->hw.dmahandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) iounmap(hc->hw.pci_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * set mode (NT or TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) hfcpci_setmode(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (hc->hw.protocol == ISDN_P_NT_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) hc->hw.states = 1; /* G1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) hc->hw.states = 2; /* F2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * function called to reset the HFC PCI chip. A complete software reset of chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * and fifos is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reset_hfcpci(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u_char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) printk(KERN_DEBUG "reset_hfcpci: entered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val = Read_hfc(hc, HFCPCI_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* enable memory mapped ports, disable busmaster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) disable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* enable memory ports + busmaster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_write_config_word(hc->pdev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PCI_ENA_MEMIO + PCI_ENA_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = Read_hfc(hc, HFCPCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hc->hw.cirm = HFCPCI_RESET; /* Reset On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mdelay(10); /* Timeout 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hc->hw.cirm = 0; /* Reset Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = Read_hfc(hc, HFCPCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) while (cnt < 50000) { /* max 50000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cnt += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val = Read_hfc(hc, HFCPCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!(val & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hc->hw.fifo_en = 0x30; /* only D fifos enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) hc->hw.bswapped = 0; /* no exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hc->hw.sctrl_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) hc->hw.mst_m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (test_bit(HFC_CFG_MASTER, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Clear already pending ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val = Read_hfc(hc, HFCPCI_INT_S1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* set NT/TE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) hfcpci_setmode(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Init GCI/IOM2 in master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Slots 0 and 1 are set for B-chan 1 and 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * D- and monitor/CI channel are not enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * STIO2 is used as data input, B1+B2 from IOM->ST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * ST B-channel send disabled -> continuous 1s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * The IOM slots are always enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* set data flow directions: connect B1,B2: HFC to/from PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hc->hw.conn = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) hc->hw.conn = 0x36; /* set data flow directions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val = Read_hfc(hc, HFCPCI_INT_S2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Timer function called when kernel timer expires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) hfcpci_Timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct hfc_pci *hc = from_timer(hc, t, hw.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hc->hw.timer.expires = jiffies + 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* WD RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * add_timer(&hc->hw.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * select a b-channel entry matching and active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct bchannel *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) Sel_BCS(struct hfc_pci *hc, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (hc->bch[0].nr & channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return &hc->bch[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (hc->bch[1].nr & channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return &hc->bch[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * clear the desired B-channel rx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u_char fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct bzfifo *bzr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (fifo_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hc->hw.fifo_en ^= fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hc->hw.last_bfifo_cnt[fifo] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bzr->f1 = MAX_B_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bzr->f2 = bzr->f1; /* init F pointers to remain constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (fifo_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) hc->hw.fifo_en |= fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * clear the desired B-channel tx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u_char fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct bzfifo *bzt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (fifo_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hc->hw.fifo_en ^= fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "z1(%x) z2(%x) state(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fifo, bzt->f1, bzt->f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fifo_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bzt->f2 = MAX_B_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bzt->f1 = bzt->f2; /* init F pointers to remain constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (fifo_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) hc->hw.fifo_en |= fifo_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fifo, bzt->f1, bzt->f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * read a complete B-frame out of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u_char *bdata, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u_char *ptr, *ptr1, new_f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int maxlen, new_z2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct zt *zp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) printk(KERN_DEBUG "hfcpci_empty_fifo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) zp = &bz->za[bz->f2]; /* point to Z-Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) new_z2 -= B_FIFO_SIZE; /* buffer wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (bch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "invalid length %d or crc\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bch->err_inv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bz->za[new_f2].z2 = cpu_to_le16(new_z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bz->f2 = new_f2; /* next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!bch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) printk(KERN_WARNING "HFCPCI: receive out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) count -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ptr = skb_put(bch->rx_skb, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) maxlen = count; /* complete transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) maxlen = B_FIFO_SIZE + B_SUB_VAL -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) le16_to_cpu(zp->z2); /* maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* start of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) memcpy(ptr, ptr1, maxlen); /* copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) count -= maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (count) { /* rest remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ptr += maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ptr1 = bdata; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) memcpy(ptr, ptr1, count); /* rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bz->za[new_f2].z2 = cpu_to_le16(new_z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bz->f2 = new_f2; /* next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) recv_Bchannel(bch, MISDN_ID_ANY, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * D-channel receive procedure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) receive_dmsg(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct dchannel *dch = &hc->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int rcnt, total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int count = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u_char *ptr, *ptr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct dfifo *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct zt *zp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) zp = &df->za[df->f2 & D_FREG_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (rcnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rcnt += D_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (dch->debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) df->f1, df->f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) le16_to_cpu(zp->z1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) le16_to_cpu(zp->z2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (df->data[le16_to_cpu(zp->z1)])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (dch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "empty_fifo hfcpci packet inv. len "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "%d or crc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) df->data[le16_to_cpu(zp->z1)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cs->err_rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (MAX_D_FRAMES + 1); /* next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) df->za[df->f2 & D_FREG_MASK].z2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (D_FIFO_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "HFC-PCI: D receive out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) total = rcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rcnt -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ptr = skb_put(dch->rx_skb, rcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) maxlen = rcnt; /* complete transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ptr1 = df->data + le16_to_cpu(zp->z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* start of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) memcpy(ptr, ptr1, maxlen); /* copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rcnt -= maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (rcnt) { /* rest remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ptr += maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ptr1 = df->data; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) memcpy(ptr, ptr1, rcnt); /* rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (MAX_D_FRAMES + 1); /* next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) recv_Dchannel(dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * check for transparent receive data and read max one 'poll' size if avail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct bzfifo *txbz, u_char *bdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) __le16 *z1r, *z2r, *z1t, *z2t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int new_z2, fcnt_rx, fcnt_tx, maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u_char *ptr, *ptr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) z2r = z1r + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) z1t = &txbz->za[MAX_B_FRAMES].z1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) z2t = z1t + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!fcnt_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return; /* no data avail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (fcnt_rx <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) new_z2 -= B_FIFO_SIZE; /* buffer wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (fcnt_tx <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fcnt_tx += B_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* fcnt_tx contains available bytes in tx-fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fcnt_tx = B_FIFO_SIZE - fcnt_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* remaining bytes to send (bytes in tx-fifo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (test_bit(FLG_RX_OFF, &bch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bch->dropcnt += fcnt_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *z2r = cpu_to_le16(new_z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (maxlen < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pr_warn("B%d: No bufferspace for %d bytes\n", bch->nr, fcnt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ptr = skb_put(bch->rx_skb, fcnt_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) maxlen = fcnt_rx; /* complete transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* start of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) memcpy(ptr, ptr1, maxlen); /* copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) fcnt_rx -= maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (fcnt_rx) { /* rest remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ptr += maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ptr1 = bdata; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) memcpy(ptr, ptr1, fcnt_rx); /* rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *z2r = cpu_to_le16(new_z2); /* new position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * B-channel main receive routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) main_rec_hfcpci(struct bchannel *bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int rcnt, real_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int receive = 0, count = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct bzfifo *txbz, *rxbz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u_char *bdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct zt *zp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if ((bch->nr & 2) && (!hc->hw.bswapped)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) real_fifo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) real_fifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) Begin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (rxbz->f1 != rxbz->f2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) bch->nr, rxbz->f1, rxbz->f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) zp = &rxbz->za[rxbz->f2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (rcnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rcnt += B_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bch->nr, le16_to_cpu(zp->z1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) le16_to_cpu(zp->z2), rcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rcnt = rxbz->f1 - rxbz->f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (rcnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rcnt += MAX_B_FRAMES + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) hfcpci_clear_fifo_rx(hc, real_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (rcnt > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) receive = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) receive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (count && receive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto Begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * D-channel send routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) hfcpci_fill_dfifo(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct dchannel *dch = &hc->dch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int count, new_z1, maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct dfifo *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u_char *src, *dst, new_f1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) printk(KERN_DEBUG "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!dch->tx_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) count = dch->tx_skb->len - dch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (dch->debug & DEBUG_HW_DFIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) df->f1, df->f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) fcnt = df->f1 - df->f2; /* frame count actually buffered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (fcnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (fcnt > (MAX_D_FRAMES - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (dch->debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "hfcpci_fill_Dfifo more as 14 frames\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #ifdef ERROR_STATISTIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) cs->err_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* now determine free bytes in FIFO buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (maxlen <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) maxlen += D_FIFO_SIZE; /* count now contains available bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (dch->debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) count, maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (count > maxlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (dch->debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) (D_FIFO_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* end fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (maxlen > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) maxlen = count; /* limit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) memcpy(dst, src, maxlen); /* first copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) count -= maxlen; /* remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dst = df->data; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) src += maxlen; /* new position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) memcpy(dst, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* for next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* new pos actual buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) df->f1 = new_f1; /* next frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dch->tx_idx = dch->tx_skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * B-channel send routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) hfcpci_fill_fifo(struct bchannel *bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int maxlen, fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int count, new_z1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct bzfifo *bz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u_char *bdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u_char new_f1, *src, *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __le16 *z1t, *z2t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) printk(KERN_DEBUG "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if ((!bch->tx_skb) || bch->tx_skb->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!test_bit(FLG_FILLEMPTY, &bch->Flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) !test_bit(FLG_TRANSPARENT, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) count = HFCPCI_FILLEMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) count = bch->tx_skb->len - bch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if ((bch->nr & 2) && (!hc->hw.bswapped)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) z1t = &bz->za[MAX_B_FRAMES].z1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) z2t = z1t + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) le16_to_cpu(*z1t), le16_to_cpu(*z2t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (fcnt <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fcnt += B_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* fcnt contains available bytes in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (count > fcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) count = fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) new_z1 = le16_to_cpu(*z1t) + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* new buffer Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) new_z1 -= B_FIFO_SIZE; /* buffer wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* end of fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (bch->debug & DEBUG_HW_BFIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) printk(KERN_DEBUG "hfcpci_FFt fillempty "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fcnt, maxlen, new_z1, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (maxlen > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) maxlen = count; /* limit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) memset(dst, bch->fill[0], maxlen); /* first copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) count -= maxlen; /* remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dst = bdata; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) memset(dst, bch->fill[0], count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *z1t = cpu_to_le16(new_z1); /* now send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* fcnt contains available bytes in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fcnt = B_FIFO_SIZE - fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* remaining bytes to send (bytes in fifo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) next_t_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) count = bch->tx_skb->len - bch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* maximum fill shall be poll*2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (count > (poll << 1) - fcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) count = (poll << 1) - fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* data is suitable for fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) new_z1 = le16_to_cpu(*z1t) + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* new buffer Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) new_z1 -= B_FIFO_SIZE; /* buffer wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) src = bch->tx_skb->data + bch->tx_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* source pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* end of fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (bch->debug & DEBUG_HW_BFIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "maxl(%d) nz1(%x) dst(%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) fcnt, maxlen, new_z1, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) fcnt += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) bch->tx_idx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (maxlen > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) maxlen = count; /* limit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) memcpy(dst, src, maxlen); /* first copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) count -= maxlen; /* remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dst = bdata; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) src += maxlen; /* new position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) memcpy(dst, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *z1t = cpu_to_le16(new_z1); /* now send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (bch->tx_idx < bch->tx_skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_kfree_skb(bch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (get_next_bframe(bch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto next_t_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __func__, bch->nr, bz->f1, bz->f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) bz->za[bz->f1].z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (fcnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (fcnt > (MAX_B_FRAMES - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "hfcpci_fill_Bfifo more as 14 frames\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* now determine free bytes in FIFO buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) le16_to_cpu(bz->za[bz->f1].z1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (maxlen <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) maxlen += B_FIFO_SIZE; /* count now contains available bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) bch->nr, count, maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (maxlen < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* new buffer Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) new_z1 -= B_FIFO_SIZE; /* buffer wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* end fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (maxlen > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) maxlen = count; /* limit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) memcpy(dst, src, maxlen); /* first copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) count -= maxlen; /* remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dst = bdata; /* start of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) src += maxlen; /* new position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) memcpy(dst, src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) bz->f1 = new_f1; /* next frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_kfree_skb(bch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) get_next_bframe(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * handle L1 state changes TE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ph_state_te(struct dchannel *dch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (dch->debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) printk(KERN_DEBUG "%s: TE newstate %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __func__, dch->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) switch (dch->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) l1_event(dch->l1, HW_RESET_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) l1_event(dch->l1, HW_DEACT_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) l1_event(dch->l1, ANYSIGNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) l1_event(dch->l1, INFO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) l1_event(dch->l1, INFO4_P8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * handle L1 state changes NT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) handle_nt_timer3(struct dchannel *dch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hc->hw.nt_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) test_and_set_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (test_bit(HFC_CFG_MASTER, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hc->hw.mst_m |= HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ph_state_nt(struct dchannel *dch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (dch->debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) printk(KERN_DEBUG "%s: NT newstate %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) __func__, dch->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) switch (dch->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (hc->hw.nt_timer < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) hc->hw.nt_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Clear already pending ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) (void) Read_hfc(hc, HFCPCI_INT_S1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) Write_hfc(hc, HFCPCI_STATES, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dch->state = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } else if (hc->hw.nt_timer == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hc->hw.nt_timer = NT_T1_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) hc->hw.ctmt |= HFCPCI_TIM3_125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) HFCPCI_CLTIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* allow G2 -> G3 transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) hc->hw.nt_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) hc->hw.mst_m &= ~HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) hc->hw.nt_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!test_and_clear_bit(FLG_L2_ACTIVATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) handle_nt_timer3(dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) hc->hw.nt_timer = NT_T3_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) hc->hw.ctmt |= HFCPCI_TIM3_125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) HFCPCI_CLTIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ph_state(struct dchannel *dch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (hc->hw.protocol == ISDN_P_NT_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) hc->hw.nt_timer < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) handle_nt_timer3(dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ph_state_nt(dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ph_state_te(dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Layer 1 callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) hfc_l1callback(struct dchannel *dch, u_int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) case INFO3_P8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) case INFO3_P10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (test_bit(HFC_CFG_MASTER, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) hc->hw.mst_m |= HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case HW_RESET_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* HFC ST 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) udelay(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (test_bit(HFC_CFG_MASTER, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) hc->hw.mst_m |= HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) HFCPCI_DO_ACTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) l1_event(dch->l1, HW_POWERUP_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case HW_DEACT_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) hc->hw.mst_m &= ~HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) skb_queue_purge(&dch->squeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (dch->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev_kfree_skb(dch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dch->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev_kfree_skb(dch->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dch->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) del_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case HW_POWERUP_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) case PH_ACTIVATE_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) test_and_set_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case PH_DEACTIVATE_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (dch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) printk(KERN_DEBUG "%s: unknown command %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) tx_birq(struct bchannel *bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) hfcpci_fill_fifo(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_kfree_skb(bch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (get_next_bframe(bch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) hfcpci_fill_fifo(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) tx_dirq(struct dchannel *dch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) hfcpci_fill_dfifo(dch->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_kfree_skb(dch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (get_next_dframe(dch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) hfcpci_fill_dfifo(dch->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) hfcpci_int(int intno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct hfc_pci *hc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u_char exval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct bchannel *bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u_char val, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) spin_lock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!(hc->hw.int_m2 & 0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) spin_unlock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return IRQ_NONE; /* not initialised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) stat = Read_hfc(hc, HFCPCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (HFCPCI_ANYINT & stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) val = Read_hfc(hc, HFCPCI_INT_S1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (hc->dch.debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) spin_unlock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) hc->irqcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (hc->dch.debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) val &= hc->hw.int_m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (val & 0x40) { /* state machine irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (hc->dch.debug & DEBUG_HW_DCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) printk(KERN_DEBUG "ph_state chg %d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) hc->dch.state, exval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) hc->dch.state = exval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) schedule_event(&hc->dch, FLG_PHCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) val &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (val & 0x80) { /* timer irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (hc->hw.protocol == ISDN_P_NT_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if ((--hc->hw.nt_timer) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) schedule_event(&hc->dch, FLG_PHCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) val &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (val & 0x08) { /* B1 rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) main_rec_hfcpci(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) else if (hc->dch.debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (val & 0x10) { /* B2 rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) bch = Sel_BCS(hc, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) main_rec_hfcpci(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) else if (hc->dch.debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (val & 0x01) { /* B1 tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) tx_birq(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) else if (hc->dch.debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (val & 0x02) { /* B2 tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bch = Sel_BCS(hc, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) tx_birq(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) else if (hc->dch.debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (val & 0x20) /* D rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) receive_dmsg(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (val & 0x04) { /* D tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) del_timer(&hc->dch.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) tx_dirq(&hc->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) spin_unlock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * timer callback for D-chan busy resolution. Currently no function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) hfcpci_dbusy_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * activate/deactivate hardware for selected channels and mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mode_hfcpci(struct bchannel *bch, int bc, int protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) int fifo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u_char rx_slot = 0, tx_slot = 0, pcm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) bch->state, protocol, bch->nr, bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) fifo2 = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) pcm_mode = (bc >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (pcm_mode) { /* PCM SLOT USE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!test_bit(HFC_CFG_PCM, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "%s: pcm channel id without HFC_CFG_PCM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) rx_slot = (bc >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) tx_slot = (bc >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) bc = bc & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (hc->chanlimit > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) hc->hw.bswapped = 0; /* B1 and B2 normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) hc->hw.sctrl_e &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (bc & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (protocol != ISDN_P_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) hc->hw.bswapped = 1; /* B1 and B2 exchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) hc->hw.sctrl_e |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) hc->hw.bswapped = 0; /* B1 and B2 normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) hc->hw.sctrl_e &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) fifo2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) hc->hw.bswapped = 0; /* B1 and B2 normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) hc->hw.sctrl_e &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) switch (protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case (-1): /* used for init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) bch->state = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) bch->nr = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case (ISDN_P_NONE):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (bch->state == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (bc & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) hc->hw.sctrl &= ~SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) hc->hw.sctrl &= ~SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (fifo2 & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) HFCPCI_INTS_B2REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) HFCPCI_INTS_B1REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (bch->nr & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) hc->hw.cirm &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) hc->hw.cirm &= 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) bch->state = ISDN_P_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) bch->nr = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) test_and_clear_bit(FLG_HDLC, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case (ISDN_P_B_RAW):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) bch->state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) bch->nr = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (bc & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) hc->hw.sctrl |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hc->hw.sctrl_r |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) hc->hw.cirm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) hc->hw.sctrl |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) hc->hw.sctrl_r |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) hc->hw.cirm |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (fifo2 & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (!tics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) HFCPCI_INTS_B2REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) hc->hw.ctmt |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) hc->hw.conn &= ~0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (!tics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) HFCPCI_INTS_B1REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) hc->hw.ctmt |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) hc->hw.conn &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case (ISDN_P_B_HDLC):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) bch->state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) bch->nr = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (bc & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) hc->hw.sctrl |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) hc->hw.sctrl_r |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) hc->hw.sctrl |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) hc->hw.sctrl_r |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (fifo2 & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) hc->hw.last_bfifo_cnt[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) HFCPCI_INTS_B2REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) hc->hw.ctmt &= ~2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) hc->hw.conn &= ~0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) hc->hw.last_bfifo_cnt[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) HFCPCI_INTS_B1REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) hc->hw.ctmt &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) hc->hw.conn &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) test_and_set_bit(FLG_HDLC, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) printk(KERN_DEBUG "prot not known %x\n", protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return -ENOPROTOOPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if ((protocol == ISDN_P_NONE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) (protocol == -1)) { /* init case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) rx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) tx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) rx_slot |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) tx_slot |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) rx_slot |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) tx_slot |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (bc & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) hc->hw.conn &= 0xc7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) hc->hw.conn |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) __func__, tx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) __func__, rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) hc->hw.conn &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) hc->hw.conn |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) __func__, tx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) __func__, rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (bch->debug & DEBUG_HW_BCHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) bch->state, protocol, bch->nr, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (bch->nr != chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) "HFCPCI rxtest wrong channel parameter %x/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) bch->nr, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) switch (protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case (ISDN_P_B_RAW):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) bch->state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (chan & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) hc->hw.sctrl_r |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!tics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) hc->hw.ctmt |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) hc->hw.conn &= ~0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) hc->hw.cirm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) hc->hw.sctrl_r |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (!tics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) hc->hw.ctmt |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) hc->hw.conn &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) hc->hw.cirm |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) case (ISDN_P_B_HDLC):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) bch->state = protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (chan & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) hc->hw.sctrl_r |= SCTRL_B2_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) hc->hw.last_bfifo_cnt[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) hc->hw.ctmt &= ~2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hc->hw.conn &= ~0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) hc->hw.sctrl_r |= SCTRL_B1_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) hc->hw.last_bfifo_cnt[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) hc->hw.ctmt &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) hc->hw.conn &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) printk(KERN_DEBUG "prot not known %x\n", protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -ENOPROTOOPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #ifdef REVERSE_BITORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) deactivate_bchannel(struct bchannel *bch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) mISDN_clear_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * Layer 1 B-channel hardware access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return mISDN_ctrl_bchannel(bch, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (bch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) case HW_TESTRX_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) case HW_TESTRX_HDLC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) case HW_TESTRX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) test_and_clear_bit(FLG_OPEN, &bch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) deactivate_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ch->protocol = ISDN_P_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ch->peer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = channel_bctrl(bch, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) printk(KERN_WARNING "%s: unknown prim(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * Layer2 -> Layer 1 Dchannel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct dchannel *dch = container_of(dev, struct dchannel, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct mISDNhead *hh = mISDN_HEAD_P(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) switch (hh->prim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) case PH_DATA_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ret = dchannel_senddata(dch, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (ret > 0) { /* direct TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) id = hh->id; /* skb can be freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) hfcpci_fill_dfifo(dch->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case PH_ACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (hc->hw.protocol == ISDN_P_NT_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (test_bit(HFC_CFG_MASTER, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) hc->hw.mst_m |= HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (test_bit(FLG_ACTIVE, &dch->Flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) HFCPCI_DO_ACTION | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ret = l1_event(dch->l1, hh->prim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) case PH_DEACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (hc->hw.protocol == ISDN_P_NT_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* prepare deactivation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) Write_hfc(hc, HFCPCI_STATES, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) skb_queue_purge(&dch->squeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (dch->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dev_kfree_skb(dch->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dch->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dch->tx_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (dch->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_kfree_skb(dch->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dch->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) del_timer(&dch->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #ifdef FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) dchannel_sched_event(&hc->dch, D_CLEARBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) hc->hw.mst_m &= ~HFCPCI_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ret = l1_event(dch->l1, hh->prim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * Layer2 -> Layer 1 Bchannel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct bchannel *bch = container_of(ch, struct bchannel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct hfc_pci *hc = bch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct mISDNhead *hh = mISDN_HEAD_P(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) switch (hh->prim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case PH_DATA_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = bchannel_senddata(bch, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ret > 0) { /* direct TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) hfcpci_fill_fifo(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) case PH_ACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret = mode_hfcpci(bch, bch->nr, ch->protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) case PH_DEACTIVATE_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) deactivate_bchannel(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * called for card init message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) inithfcpci(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) printk(KERN_DEBUG "inithfcpci: entered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) hc->chanlimit = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mode_hfcpci(&hc->bch[0], 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) mode_hfcpci(&hc->bch[1], 2, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) init_card(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) int cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) printk(KERN_DEBUG "init_card: entered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) disable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) "mISDN: couldn't get interrupt %d\n", hc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) reset_hfcpci(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) while (cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) inithfcpci(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * Finally enable IRQ output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * this is only allowed, if an IRQ routine is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * established for this HFC, so don't do that earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) enable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Timeout 80ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) schedule_timeout((80 * HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) hc->irq, hc->irqcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* now switch timer interrupt off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* reinit mode reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (!hc->irqcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) "HFC PCI: IRQ(%d) getting no interrupts "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) "during init %d\n", hc->irq, 4 - cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (cnt == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) reset_hfcpci(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) hc->initdone = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) disable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) free_irq(hc->irq, hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u_char slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) switch (cq->op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) case MISDN_CTRL_GETOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case MISDN_CTRL_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* channel 0 disabled loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (cq->channel < 0 || cq->channel > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (cq->channel & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) slot = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) slot = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) __func__, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) Write_hfc(hc, HFCPCI_B1_SSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) Write_hfc(hc, HFCPCI_B1_RSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) hc->hw.conn = (hc->hw.conn & ~7) | 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (cq->channel & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) slot = 0xC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) slot = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) __func__, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) Write_hfc(hc, HFCPCI_B2_SSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) Write_hfc(hc, HFCPCI_B2_RSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (cq->channel & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) hc->hw.trm |= 0x80; /* enable IOM-loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hc->hw.trm &= 0x7f; /* disable IOM-loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) case MISDN_CTRL_CONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (cq->channel == cq->p1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (cq->channel < 1 || cq->channel > 2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) cq->p1 < 1 || cq->p1 > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) slot = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) slot = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) __func__, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) Write_hfc(hc, HFCPCI_B1_SSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) Write_hfc(hc, HFCPCI_B2_RSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) slot = 0xC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) slot = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) __func__, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) Write_hfc(hc, HFCPCI_B2_SSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) Write_hfc(hc, HFCPCI_B1_RSL, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) hc->hw.trm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) case MISDN_CTRL_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) hc->hw.trm &= 0x7f; /* disable IOM-loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) case MISDN_CTRL_L1_TIMER3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) printk(KERN_WARNING "%s: unknown Op %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) __func__, cq->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) struct channel_req *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (debug & DEBUG_HW_OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) hc->dch.dev.id, __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (rq->protocol == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (rq->adr.channel == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* TODO: E-Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (!hc->initdone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (rq->protocol == ISDN_P_TE_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) err = create_l1(&hc->dch, hfc_l1callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) hc->hw.protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ch->protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) err = init_card(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (rq->protocol != ch->protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (hc->hw.protocol == ISDN_P_TE_S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) l1_event(hc->dch.l1, CLOSE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (rq->protocol == ISDN_P_TE_S0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) err = create_l1(&hc->dch, hfc_l1callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) hc->hw.protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ch->protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) hfcpci_setmode(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) 0, NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) rq->ch = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (!try_module_get(THIS_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) printk(KERN_WARNING "%s:cannot get module\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct bchannel *bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (rq->adr.channel == 0 || rq->adr.channel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (rq->protocol == ISDN_P_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) bch = &hc->bch[rq->adr.channel - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (test_and_set_bit(FLG_OPEN, &bch->Flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) return -EBUSY; /* b-channel can be only open once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) bch->ch.protocol = rq->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) rq->ch = &bch->ch; /* TODO: E-channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!try_module_get(THIS_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) printk(KERN_WARNING "%s:cannot get module\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * device control function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct dchannel *dch = container_of(dev, struct dchannel, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct hfc_pci *hc = dch->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct channel_req *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (dch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) printk(KERN_DEBUG "%s: cmd:%x %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) __func__, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) case OPEN_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) rq = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if ((rq->protocol == ISDN_P_TE_S0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) (rq->protocol == ISDN_P_NT_S0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) err = open_dchannel(hc, ch, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) err = open_bchannel(hc, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) case CLOSE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (debug & DEBUG_HW_OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) __func__, hc->dch.dev.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case CONTROL_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) err = channel_ctrl(hc, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (dch->debug & DEBUG_HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) printk(KERN_DEBUG "%s: unknown command %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) setup_hw(struct hfc_pci *hc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) hc->hw.cirm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) hc->dch.state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) pci_set_master(hc->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!hc->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) hc->hw.pci_io =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (!hc->hw.pci_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* Allocate memory for FIFOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* the memory needs to be on a 32k boundary within the first 4G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (dma_set_mask(&hc->pdev->dev, 0xFFFF8000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "HFC-PCI: No usable DMA configuration!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) buffer = dma_alloc_coherent(&hc->pdev->dev, 0x8000, &hc->hw.dmahandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* We silently assume the address is okay if nonzero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) "HFC-PCI: Error allocating memory for FIFO!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) hc->hw.fifos = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (unlikely(!hc->hw.pci_io)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) "HFC-PCI: Error in ioremap for PCI!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) hc->hw.dmahandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "HFC-PCI: defined at mem %#lx fifo %p(%pad) IRQ %d HZ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) (u_long) hc->hw.pci_io, hc->hw.fifos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) &hc->hw.dmahandle, hc->irq, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* enable memory mapped ports, disable busmaster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) hc->hw.int_m2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) disable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) hc->hw.int_m1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* At this point the needed PCI config is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* fifos are still not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) timer_setup(&hc->hw.timer, hfcpci_Timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /* default PCM master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) release_card(struct hfc_pci *hc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) spin_lock_irqsave(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) hc->hw.int_m2 = 0; /* interrupt output off ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) disable_hwirq(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (hc->dch.timer.function != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) del_timer(&hc->dch.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) hc->dch.timer.function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) spin_unlock_irqrestore(&hc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (hc->hw.protocol == ISDN_P_TE_S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) l1_event(hc->dch.l1, CLOSE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (hc->initdone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) free_irq(hc->irq, hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) release_io_hfcpci(hc); /* must release after free_irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) mISDN_unregister_device(&hc->dch.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) mISDN_freebchannel(&hc->bch[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) mISDN_freebchannel(&hc->bch[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) mISDN_freedchannel(&hc->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) pci_set_drvdata(hc->pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) kfree(hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) setup_card(struct hfc_pci *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) u_int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) char name[MISDN_MAX_IDLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) card->dch.debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) spin_lock_init(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) card->dch.hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) card->dch.dev.D.send = hfcpci_l2l1D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) card->dch.dev.D.ctrl = hfc_dctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) card->dch.dev.nrbchan = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) card->bch[i].nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) set_channelmap(i + 1, card->dch.dev.channelmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) card->bch[i].debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) card->bch[i].hw = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) card->bch[i].ch.send = hfcpci_l2l1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) card->bch[i].ch.ctrl = hfc_bctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) card->bch[i].ch.nr = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) err = setup_hw(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) HFC_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) mISDN_freebchannel(&card->bch[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) mISDN_freebchannel(&card->bch[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) mISDN_freedchannel(&card->dch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /* private data in the PCI devices list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct _hfc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) u_int subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u_int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static const struct _hfc_map hfc_map[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {HFC_CCD_B000, 0, "Billion B000"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) {HFC_CCD_B006, 0, "Billion B006"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {HFC_CCD_B007, 0, "Billion B007"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {HFC_CCD_B008, 0, "Billion B008"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) {HFC_CCD_B009, 0, "Billion B009"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) {HFC_CCD_B00A, 0, "Billion B00A"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) {HFC_CCD_B00B, 0, "Billion B00B"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) {HFC_CCD_B00C, 0, "Billion B00C"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) {HFC_CCD_B100, 0, "Seyeon B100"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) {HFC_CCD_B700, 0, "Primux II S0 B700"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) {HFC_BERKOM_A1T, 0, "German telekom A1T"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) {HFC_DIGI_DF_M_IOM2_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) "Digi International DataFire Micro V IOM2 (Europe)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {HFC_DIGI_DF_M_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "Digi International DataFire Micro V (Europe)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) {HFC_DIGI_DF_M_IOM2_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) "Digi International DataFire Micro V IOM2 (North America)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) {HFC_DIGI_DF_M_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) "Digi International DataFire Micro V (North America)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static const struct pci_device_id hfc_ids[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) (unsigned long) &hfc_map[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) (unsigned long) &hfc_map[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) (unsigned long) &hfc_map[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) (unsigned long) &hfc_map[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) (unsigned long) &hfc_map[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) (unsigned long) &hfc_map[5] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) (unsigned long) &hfc_map[6] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) (unsigned long) &hfc_map[7] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) (unsigned long) &hfc_map[8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) (unsigned long) &hfc_map[9] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) (unsigned long) &hfc_map[10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) (unsigned long) &hfc_map[11] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) (unsigned long) &hfc_map[12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) (unsigned long) &hfc_map[13] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) (unsigned long) &hfc_map[14] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) (unsigned long) &hfc_map[15] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) (unsigned long) &hfc_map[16] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) (unsigned long) &hfc_map[17] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) (unsigned long) &hfc_map[18] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) (unsigned long) &hfc_map[19] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) (unsigned long) &hfc_map[20] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) (unsigned long) &hfc_map[21] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) (unsigned long) &hfc_map[22] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) struct hfc_pci *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) card = kzalloc(sizeof(struct hfc_pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) printk(KERN_ERR "No kmem for HFC card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) card->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) card->subtype = m->subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) m->name, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) card->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) err = setup_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) hfc_remove_pci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct hfc_pci *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) release_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) printk(KERN_DEBUG "%s: drvdata already removed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) static struct pci_driver hfc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "hfcpci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .probe = hfc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .remove = hfc_remove_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .id_table = hfc_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) _hfcpci_softirq(struct device *dev, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct hfc_pci *hc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct bchannel *bch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (hc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) spin_lock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) main_rec_hfcpci(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) tx_birq(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) main_rec_hfcpci(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) tx_birq(bch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) spin_unlock(&hc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) hfcpci_softirq(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) _hfcpci_softirq) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* if next event would be in the past ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) hfc_jiffies = jiffies + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) hfc_jiffies += tics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) hfc_tl.expires = hfc_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) add_timer(&hfc_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) HFC_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) if (!poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) poll = HFCPCI_BTRANS_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (poll != HFCPCI_BTRANS_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) tics = (poll * HZ) / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) if (tics < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) tics = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) poll = (tics * 8000) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) if (poll > 256 || poll < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) printk(KERN_ERR "%s: Wrong poll value %d not in range "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) "of 8..256.\n", __func__, poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (poll != HFCPCI_BTRANS_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) printk(KERN_INFO "%s: Using alternative poll value of %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) __func__, poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) timer_setup(&hfc_tl, hfcpci_softirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) hfc_tl.expires = jiffies + tics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) hfc_jiffies = hfc_tl.expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) add_timer(&hfc_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) tics = 0; /* indicate the use of controller's timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) err = pci_register_driver(&hfc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (timer_pending(&hfc_tl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) del_timer(&hfc_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) HFC_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (timer_pending(&hfc_tl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) del_timer_sync(&hfc_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pci_unregister_driver(&hfc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) module_init(HFC_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) module_exit(HFC_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) MODULE_DEVICE_TABLE(pci, hfc_ids);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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