^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/soc/qcom/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDC_MAX_IRQS 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDC_MAX_GPIO_IRQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ENABLE_INTR(reg, intr) (reg | (1 << intr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_ENABLE_BANK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_i_CFG 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PDC_NO_PARENT_IRQ ~0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct pdc_pin_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 parent_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct spi_cfg_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bool scm_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static DEFINE_RAW_SPINLOCK(pdc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void __iomem *pdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct pdc_pin_region *pdc_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int pdc_region_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct spi_cfg_regs *spi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void pdc_reg_write(int reg, u32 i, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u32 pdc_reg_read(int reg, u32 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return readl_relaxed(pdc_base + reg + i * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void pdc_enable_intr(struct irq_data *d, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int pin_out = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 index, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) index = pin_out / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mask = pin_out % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) raw_spin_lock_irqsave(&pdc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) raw_spin_unlock_irqrestore(&pdc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void qcom_pdc_gic_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pdc_enable_intr(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq_chip_disable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void qcom_pdc_gic_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pdc_enable_intr(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_chip_enable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static u32 __spi_pin_read(unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *cfg_reg = spi_cfg->base + pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 scm_cfg_reg = spi_cfg->start + pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (spi_cfg->scm_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) qcom_scm_io_readl(scm_cfg_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return readl(cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void __spi_pin_write(unsigned int pin, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *cfg_reg = spi_cfg->base + pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u64 scm_cfg_reg = spi_cfg->start + pin * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (spi_cfg->scm_io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) qcom_scm_io_writel(scm_cfg_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(val, cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int spi = hwirq - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 pin = spi / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 mask = BIT(spi % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!spi_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (pin * 4 > spi_cfg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) raw_spin_lock_irqsave(&pdc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = __spi_pin_read(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __spi_pin_write(pin, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) raw_spin_unlock_irqrestore(&pdc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * GIC does not handle falling edge or active low. To allow falling edge and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * active low interrupts to be handled at GIC, PDC has an inverter that inverts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * falling edge into a rising edge and active low into an active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * set as per the table below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Level sensitive active low LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Rising edge sensitive NOT USED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Falling edge sensitive LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Dual Edge sensitive NOT USED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Level sensitive active High HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Falling Edge sensitive NOT USED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Rising edge sensitive HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Dual Edge sensitive HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum pdc_irq_config_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PDC_LEVEL_LOW = 0b000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PDC_EDGE_FALLING = 0b010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PDC_LEVEL_HIGH = 0b100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PDC_EDGE_RISING = 0b110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PDC_EDGE_DUAL = 0b111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * qcom_pdc_gic_set_type: Configure PDC for the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @d: the interrupt data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @type: the interrupt type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * If @type is edge triggered, forward that as Rising edge as PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * takes care of converting falling edge to rising edge signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * If @type is level, then forward that as level high as PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * takes care of converting falling edge to rising edge signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int parent_hwirq = d->parent_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) enum pdc_irq_config_bits pdc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) enum pdc_irq_config_bits old_pdc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pdc_type = PDC_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pdc_type = PDC_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pdc_type = PDC_EDGE_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pdc_type = PDC_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pdc_type = PDC_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Additionally, configure (only) the GPIO in the f/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = spi_configure_type(parent_hwirq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = irq_chip_set_type_parent(d, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * When we change types the PDC can give a phantom interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Clear it. Specifically the phantom shows up when reconfiguring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * polarity of interrupt without changing the state of the signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * but let's be consistent and clear it always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * interrupt will be cleared before the rest of the system sees it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (old_pdc_type != pdc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct irq_chip qcom_pdc_gic_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "PDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .irq_disable = qcom_pdc_gic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .irq_enable = qcom_pdc_gic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .irq_get_irqchip_state = irq_chip_get_parent_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .irq_set_irqchip_state = irq_chip_set_parent_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .irq_set_type = qcom_pdc_gic_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = IRQCHIP_MASK_ON_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IRQCHIP_SKIP_SET_WAKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static irq_hw_number_t get_parent_hwirq(int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct pdc_pin_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < pdc_region_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) region = &pdc_region[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (pin >= region->pin_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pin < region->pin_base + region->cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return (region->parent_base + pin - region->pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PDC_NO_PARENT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long *hwirq, unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) irq_hw_number_t hwirq, parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) &qcom_pdc_gic_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) parent_hwirq = get_parent_hwirq(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (parent_hwirq == PDC_NO_PARENT_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return irq_domain_disconnect_hierarchy(domain->parent, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) parent_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) parent_fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) parent_fwspec.param[1] = parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) parent_fwspec.param[2] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct irq_domain_ops qcom_pdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .translate = qcom_pdc_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .alloc = qcom_pdc_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) irq_hw_number_t hwirq, parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (hwirq == GPIO_NO_WAKE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return irq_domain_disconnect_hierarchy(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &qcom_pdc_gic_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) parent_hwirq = get_parent_hwirq(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (parent_hwirq == PDC_NO_PARENT_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return irq_domain_disconnect_hierarchy(domain->parent, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) parent_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) parent_fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) parent_fwspec.param[1] = parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) parent_fwspec.param[2] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enum irq_domain_bus_token bus_token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return bus_token == DOMAIN_BUS_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct irq_domain_ops qcom_pdc_gpio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .select = qcom_pdc_gpio_domain_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .alloc = qcom_pdc_gpio_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int pdc_setup_pin_mapping(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret, n, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 irq_index, reg_index, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (n <= 0 || n % 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pdc_region_cnt = n / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!pdc_region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pdc_region_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (n = 0; n < pdc_region_cnt; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) n * 3 + 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &pdc_region[n].pin_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) n * 3 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &pdc_region[n].parent_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) n * 3 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &pdc_region[n].cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (i = 0; i < pdc_region[n].cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg_index = (i + pdc_region[n].pin_base) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) irq_index = (i + pdc_region[n].pin_base) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val &= ~BIT(irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pdc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!pdc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_err("%pOF: unable to map PDC registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pr_err("%pOF: unable to find PDC's parent domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = pdc_setup_pin_mapping(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) of_fwnode_handle(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &qcom_pdc_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!pdc_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_err("%pOF: GIC domain add failed\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = of_address_to_resource(node, 1, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!spi_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spi_cfg->scm_io = of_find_property(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "qcom,scm-spi-cfg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) spi_cfg->size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (spi_cfg->scm_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spi_cfg->start = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spi_cfg->base = ioremap(res.start, spi_cfg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!spi_cfg->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PDC_MAX_GPIO_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) of_fwnode_handle(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &qcom_pdc_gpio_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!pdc_gpio_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) irq_domain_remove(pdc_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) kfree(spi_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) kfree(pdc_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) iounmap(pdc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int qcom_pdc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct device_node *parent = of_irq_find_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return qcom_pdc_init(np, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct of_device_id qcom_pdc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { .compatible = "qcom,pdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_DEVICE_TABLE(of, qcom_pdc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct platform_driver qcom_pdc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe = qcom_pdc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "qcom-pdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .of_match_table = qcom_pdc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) module_platform_driver(qcom_pdc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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