^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Driver for interrupt combiners in the Top-level Control and Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Registers (TCSR) hardware block in Qualcomm Technologies chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * An interrupt combiner in this block combines a set of interrupts by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * OR'ing the individual interrupt signals into a summary interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * signal routed to a parent interrupt controller, and provides read-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * only, 32-bit registers to query the status of individual interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The status bit for IRQ n is bit (n % 32) within register (n / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of the given combiner. Thus, each combiner can be described as a set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of register offsets and the number of IRQs managed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pr_fmt(fmt) "QCOM80B1:" fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct combiner_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct combiner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct combiner_reg regs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline int irq_nr(u32 reg, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return reg * REG_SIZE + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Handler for the cascaded IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void combiner_handle_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct combiner *combiner = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (reg = 0; reg < combiner->nregs; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bit = readl_relaxed(combiner->regs[reg].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) status = bit & combiner->regs[reg].enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (bit && !status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) smp_processor_id(), bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) combiner->regs[reg].enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) combiner->regs[reg].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bit = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) status &= ~(1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) hwirq = irq_nr(reg, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) virq = irq_find_mapping(combiner->domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (virq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void combiner_irq_chip_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct combiner *combiner = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clear_bit(data->hwirq % REG_SIZE, ®->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void combiner_irq_chip_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct combiner *combiner = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) set_bit(data->hwirq % REG_SIZE, ®->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct irq_chip irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .irq_mask = combiner_irq_chip_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .irq_unmask = combiner_irq_chip_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "qcom-irq-combiner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) irq_domain_reset_irq_data(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long *hwirq, unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct combiner *combiner = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (is_acpi_node(fws->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (WARN_ON((fws->param_count != 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (fws->param[0] >= combiner->nirqs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (fws->param[1] & IORESOURCE_IRQ_LOWEDGE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) (fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *hwirq = fws->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *type = fws->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct irq_domain_ops domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .map = combiner_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .unmap = combiner_irq_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .translate = combiner_irq_translate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int *count = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ++(*count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int count_registers(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) count_registers_cb, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct get_registers_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct combiner *combiner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct get_registers_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct acpi_resource_generic_register *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phys_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __iomem *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = &ares->data.generic_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) paddr = reg->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if ((reg->space_id != ACPI_SPACE_MEM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (reg->bit_offset != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (reg->bit_width > REG_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctx->err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return AE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ctx->err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return AE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctx->combiner->nirqs += reg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ctx->combiner->nregs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int get_registers(struct platform_device *pdev, struct combiner *comb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct get_registers_context ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ctx.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctx.combiner = comb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ctx.err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) get_registers_cb, &ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ctx.err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int __init combiner_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct combiner *combiner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) nregs = count_registers(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (nregs <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&pdev->dev, "Error reading register resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) combiner = devm_kzalloc(&pdev->dev, struct_size(combiner, regs, nregs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!combiner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) err = get_registers(pdev, combiner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) combiner->parent_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (combiner->parent_irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) &domain_ops, combiner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!combiner->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Errors printed by irq_domain_create_linear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) irq_set_chained_handler_and_data(combiner->parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) combiner_handle_irq, combiner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct acpi_device_id qcom_irq_combiner_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { "QCOM80B1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct platform_driver qcom_irq_combiner_probe = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "qcom-irq-combiner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .probe = combiner_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) builtin_platform_driver(qcom_irq_combiner_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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