^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/irqchip/irq-zevio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IO_STATUS 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IO_RAW_STATUS 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IO_ENABLE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IO_DISABLE 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IO_CURRENT 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IO_RESET 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IO_MAX_PRIOTY 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IO_IRQ_BASE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IO_FIQ_BASE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IO_INVERT_SEL 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IO_STICKY_SEL 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IO_PRIORITY_SEL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_INTRS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FIQ_START MAX_INTRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct irq_domain *zevio_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void __iomem *zevio_irq_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void zevio_irq_ack(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct irq_chip_regs *regs = &irq_data_get_chip_type(irqd)->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) readl(gc->reg_base + regs->ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) while (readl(zevio_irq_io + IO_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irqnr = readl(zevio_irq_io + IO_CURRENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) handle_domain_irq(zevio_irq_domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __init zevio_init_irq_base(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(~0, base + IO_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Accept interrupts of all priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(0xF, base + IO_MAX_PRIOTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Reset existing interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) readl(base + IO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int __init zevio_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (WARN_ON(zevio_irq_io || zevio_irq_domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) zevio_irq_io = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BUG_ON(!zevio_irq_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Do not invert interrupt status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(~0, zevio_irq_io + IO_INVERT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Disable sticky interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(0, zevio_irq_io + IO_STICKY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* We don't use IRQ priorities. Set each IRQ to highest priority. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Init IRQ and FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) BUG_ON(!zevio_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "zevio_intc", handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clr, 0, IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BUG_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) gc = irq_get_domain_generic_chip(zevio_irq_domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gc->reg_base = zevio_irq_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gc->chip_types[0].chip.irq_ack = zevio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) set_handle_irq(zevio_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_info("TI-NSPIRE classic IRQ controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags