^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Xtensa built-in interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002 - 2013 Tensilica, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Kevin Chea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Device Tree IRQ specifier translation function which works with one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * two cell bindings. First cell value maps directly to the hwirq number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Second cell if present specifies whether hwirq number is external (1) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * internal (0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long *out_hwirq, unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return xtensa_irq_domain_xlate(intspec, intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) intspec[0], intspec[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) out_hwirq, out_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct irq_domain_ops xtensa_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .xlate = xtensa_pic_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .map = xtensa_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void xtensa_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cached_irq_mask &= ~(1 << d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) xtensa_set_sr(cached_irq_mask, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void xtensa_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cached_irq_mask |= 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) xtensa_set_sr(cached_irq_mask, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void xtensa_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) xtensa_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void xtensa_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xtensa_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void xtensa_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) xtensa_set_sr(1 << d->hwirq, intclear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int xtensa_irq_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int mask = 1u << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xtensa_set_sr(mask, intset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct irq_chip xtensa_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "xtensa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_enable = xtensa_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .irq_disable = xtensa_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .irq_mask = xtensa_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .irq_unmask = xtensa_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .irq_ack = xtensa_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_retrigger = xtensa_irq_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct irq_domain *root_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &xtensa_irq_domain_ops, &xtensa_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) irq_set_default_host(root_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int __init xtensa_pic_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct irq_domain *root_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &xtensa_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irq_set_default_host(root_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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