^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Xtensa MX interrupt distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002 - 2013 Tensilica, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mxregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HW_IRQ_IPI_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HW_IRQ_MX_BASE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HW_IRQ_EXTERN_BASE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (hw < HW_IRQ_IPI_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct irq_chip *irq_chip = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) irq_set_chip_and_handler_name(irq, irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) handle_percpu_irq, "ipi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) irq_set_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return xtensa_irq_map(d, irq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Device Tree IRQ specifier translation function which works with one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * two cell bindings. First cell value maps directly to the hwirq number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Second cell if present specifies whether hwirq number is external (1) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * internal (0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long *out_hwirq, unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return xtensa_irq_domain_xlate(intspec, intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) out_hwirq, out_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .xlate = xtensa_mx_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .map = xtensa_mx_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void secondary_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __this_cpu_write(cached_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) XCHAL_INTTYPE_MASK_EXTERN_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void xtensa_mx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int mask = 1u << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ext_irq >= HW_IRQ_MX_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mask = __this_cpu_read(cached_irq_mask) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __this_cpu_write(cached_irq_mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) xtensa_set_sr(mask, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void xtensa_mx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int mask = 1u << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ext_irq >= HW_IRQ_MX_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mask |= __this_cpu_read(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __this_cpu_write(cached_irq_mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) xtensa_set_sr(mask, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void xtensa_mx_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) xtensa_mx_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void xtensa_mx_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) xtensa_mx_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void xtensa_mx_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) xtensa_set_sr(1 << d->hwirq, intclear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int xtensa_mx_irq_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int mask = 1u << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) xtensa_set_sr(mask, intset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int xtensa_mx_irq_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct cpumask *dest, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int cpu = cpumask_any_and(dest, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned mask = 1u << cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irq_data_update_effective_affinity(d, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct irq_chip xtensa_mx_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "xtensa-mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .irq_enable = xtensa_mx_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .irq_disable = xtensa_mx_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .irq_mask = xtensa_mx_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .irq_unmask = xtensa_mx_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .irq_ack = xtensa_mx_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .irq_retrigger = xtensa_mx_irq_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .irq_set_affinity = xtensa_mx_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct irq_domain *root_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &xtensa_mx_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) &xtensa_mx_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) irq_set_default_host(root_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) secondary_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int __init xtensa_mx_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct irq_domain *root_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &xtensa_mx_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) irq_set_default_host(root_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) secondary_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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