Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012-2013 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/jump_label.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* No one else should require these constants, so define them locally here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ISR 0x00			/* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IPR 0x04			/* Interrupt Pending Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IER 0x08			/* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IAR 0x0c			/* Interrupt Acknowledge Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SIE 0x10			/* Set Interrupt Enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CIE 0x14			/* Clear Interrupt Enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IVR 0x18			/* Interrupt Vector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MER 0x1c			/* Master Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MER_ME (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MER_HIE (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct xintc_irq_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void		__iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct		irq_domain *root_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32		intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32		nr_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static struct xintc_irq_chip *primary_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (static_branch_unlikely(&xintc_is_be))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		iowrite32be(data, irqc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		iowrite32(data, irqc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (static_branch_unlikely(&xintc_is_be))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return ioread32be(irqc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return ioread32(irqc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void intc_enable_or_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned long mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* ack level irqs because they can't be acked during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * ack function since the handle_level_irq function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * acks the irq before calling the interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (irqd_is_level_type(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		xintc_write(irqc, IAR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	xintc_write(irqc, SIE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void intc_disable_or_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	xintc_write(irqc, CIE, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void intc_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	xintc_write(irqc, IAR, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void intc_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	xintc_write(irqc, CIE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	xintc_write(irqc, IAR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct irq_chip intc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.name = "Xilinx INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.irq_unmask = intc_enable_or_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.irq_mask = intc_disable_or_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.irq_ack = intc_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.irq_mask_ack = intc_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	hwirq = xintc_read(irqc, IVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (hwirq != -1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		irq = irq_find_mapping(irqc->root_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int xintc_get_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned int irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	hwirq = xintc_read(primary_intc, IVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (hwirq != -1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		irq = irq_find_mapping(primary_intc->root_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct xintc_irq_chip *irqc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (irqc->intr_mask & BIT(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		irq_set_chip_and_handler_name(irq, &intc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					      handle_edge_irq, "edge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		irq_clear_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		irq_set_chip_and_handler_name(irq, &intc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					      handle_level_irq, "level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		irq_set_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	irq_set_chip_data(irq, irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct irq_domain_ops xintc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.map = xintc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void xil_intc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct xintc_irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	irqc = irq_data_get_irq_handler_data(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		pending = xintc_get_irq_local(irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		if (pending == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		generic_handle_irq(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	} while (true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int __init xilinx_intc_of_init(struct device_node *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					     struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct xintc_irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!irqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	irqc->base = of_iomap(intc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	BUG_ON(!irqc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		irqc->intr_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (irqc->intr_mask >> irqc->nr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		intc, irqc->nr_irq, irqc->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * Disable all external interrupts until they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * explicity requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	xintc_write(irqc, IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* Acknowledge any pending interrupts just in case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	xintc_write(irqc, IAR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* Turn on the Master Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	xintc_write(irqc, MER, MER_HIE | MER_ME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		static_branch_enable(&xintc_is_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		xintc_write(irqc, MER, MER_HIE | MER_ME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 						  &xintc_irq_domain_ops, irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (!irqc->root_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		pr_err("irq-xilinx: Unable to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		irq = irq_of_parse_and_map(intc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			irq_set_chained_handler_and_data(irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 							 xil_intc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 							 irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			pr_err("irq-xilinx: interrupts property not in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		primary_intc = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		irq_set_default_host(primary_intc->root_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	iounmap(irqc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	kfree(irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);