Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  arch/arm/mach-vt8500/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This file is copied and modified from the original irq.c provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Alexey Charkov. Minor changes have been made for Device Tree Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VT8500_ICPC_IRQ		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VT8500_ICPC_FIQ		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VT8500_ICDC		0x40		/* Destination Control 64*u32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VT8500_ICIS		0x80		/* Interrupt status, 16*u32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* ICPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ICPC_MASK		0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ICPC_ROTATE		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* IC_DCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ICDC_IRQ		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ICDC_FIQ		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ICDC_DSS0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ICDC_DSS1		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ICDC_DSS2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ICDC_DSS3		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ICDC_DSS4		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ICDC_DSS5		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define VT8500_INT_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VT8500_INT_ENABLE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define VT8500_TRIGGER_HIGH	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VT8500_TRIGGER_RISING	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VT8500_TRIGGER_FALLING	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VT8500_EDGE		( VT8500_TRIGGER_RISING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				| VT8500_TRIGGER_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define VT8500_INTC_MAX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct vt8500_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem 		*base;		/* IO Memory base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct irq_domain	*domain;	/* Domain for this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Global variable for accessing io-mem addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct vt8500_irq_data intc[VT8500_INTC_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static u32 active_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void vt8500_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct vt8500_irq_data *priv = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	void __iomem *base = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u8 edge, dctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (edge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		status = readl(stat_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		status |= (1 << (d->hwirq & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		writel(status, stat_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		dctr = readb(base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		dctr &= ~VT8500_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		writeb(dctr, base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void vt8500_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct vt8500_irq_data *priv = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	void __iomem *base = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u8 dctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dctr = readb(base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dctr |= VT8500_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	writeb(dctr, base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct vt8500_irq_data *priv = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	void __iomem *base = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u8 dctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	dctr = readb(base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	dctr &= ~VT8500_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case IRQF_TRIGGER_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case IRQF_TRIGGER_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dctr |= VT8500_TRIGGER_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case IRQF_TRIGGER_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		dctr |= VT8500_TRIGGER_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case IRQF_TRIGGER_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		dctr |= VT8500_TRIGGER_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	writeb(dctr, base + VT8500_ICDC + d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct irq_chip vt8500_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.name = "vt8500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.irq_ack = vt8500_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.irq_mask = vt8500_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.irq_unmask = vt8500_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.irq_set_type = vt8500_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void __init vt8500_init_irq_hw(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Enable rotating priority for IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	writel(0x00, base + VT8500_ICPC_FIQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* Disable all interrupts and route them to IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	for (i = 0; i < 64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 							irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct irq_domain_ops vt8500_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.map = vt8500_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u32 stat, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Loop through each active controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (i=0; i<active_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		base = intc[i].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		irqnr = readl_relaxed(base) & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		  Highest Priority register default = 63, so check that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		  is a real interrupt by checking the status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (irqnr == 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			stat = readl_relaxed(base + VT8500_ICIS + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			if (!(stat & BIT(31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		handle_domain_irq(intc[i].domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int __init vt8500_irq_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				  struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct device_node *np = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (active_cnt == VT8500_INTC_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 								__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	intc[active_cnt].base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	intc[active_cnt].domain = irq_domain_add_linear(node, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			&vt8500_irq_domain_ops,	&intc[active_cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!intc[active_cnt].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		pr_err("%s: Unable to map IO memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!intc[active_cnt].domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		pr_err("%s: Unable to add irq domain!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	set_handle_irq(vt8500_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	vt8500_init_irq_hw(intc[active_cnt].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	pr_info("vt8500-irq: Added interrupt controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	active_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* check if this is a slaved controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (of_irq_count(np) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		/* check that we have the correct number of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (of_irq_count(np) != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			pr_err("%s: Incorrect IRQ map for slaved controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 					__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			irq = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);