^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/common/vic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 - 2003 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip/arm-vic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIC_IRQ_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VIC_FIQ_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VIC_RAW_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIC_INT_ENABLE_CLEAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIC_INT_SOFT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIC_INT_SOFT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIC_PROTECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIC_ITCR 0x300 /* VIC test control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIC_VECT_CNTL_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIC_PL192_VECT_ADDR 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * struct vic_device - VIC PM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @irq: The IRQ number for the base of the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @base: The register base for the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @valid_sources: A bitmask of valid interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @resume_sources: A bitmask of interrupts for resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @resume_irqs: The IRQs enabled for resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @int_select: Save for VIC_INT_SELECT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @int_enable: Save for VIC_INT_ENABLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @soft_int: Save for VIC_INT_SOFT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @protect: Save for VIC_PROTECT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @domain: The IRQ domain for the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct vic_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 valid_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 resume_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 resume_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 int_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 soft_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* we cannot allocate memory when VICs are initially registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int vic_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void vic_handle_irq(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * vic_init2 - common initialisation code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @base: Base of the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Common initialisation code for registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * and resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void vic_init2(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(VIC_VECT_CNTL_ENABLE | i, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(32, base + VIC_PL190_DEF_VECT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void resume_one_vic(struct vic_device *vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *base = vic->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* re-initialise static settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) vic_init2(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel(vic->int_select, base + VIC_INT_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(vic->protect, base + VIC_PROTECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* set the enabled ints and then clear the non-enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(vic->int_enable, base + VIC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* and the same for the soft-int register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(vic->soft_int, base + VIC_INT_SOFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void vic_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for (id = vic_id - 1; id >= 0; id--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) resume_one_vic(vic_devices + id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void suspend_one_vic(struct vic_device *vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void __iomem *base = vic->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) vic->int_select = readl(base + VIC_INT_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) vic->int_enable = readl(base + VIC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) vic->soft_int = readl(base + VIC_INT_SOFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) vic->protect = readl(base + VIC_PROTECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* set the interrupts (if any) that are used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * resuming the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(vic->resume_irqs, base + VIC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int vic_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (id = 0; id < vic_id; id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) suspend_one_vic(vic_devices + id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct syscore_ops vic_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .suspend = vic_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .resume = vic_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * vic_pm_init - initicall to register VIC pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * This is called via late_initcall() to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * the resources for the VICs due to the early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * nature of the VIC's registration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int __init vic_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (vic_id > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) register_syscore_ops(&vic_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) late_initcall(vic_pm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct irq_chip vic_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct vic_device *v = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Skip invalid IRQs, only register handlers for the real ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!(v->valid_sources & (1 << hwirq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) irq_set_chip_data(irq, v->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Handle each interrupt in a single VIC. Returns non-zero if we've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * handled at least one interrupt. This reads the status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * before handling each interrupt, which is necessary given that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 stat, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) irq = ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) handle_domain_irq(vic->domain, irq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void vic_handle_irq_cascaded(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 stat, hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct irq_chip *host_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct vic_device *vic = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) chained_irq_enter(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hwirq = ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) generic_handle_irq(irq_find_mapping(vic->domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) chained_irq_exit(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Keep iterating over all registered VIC's until there are no pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i, handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0, handled = 0; i < vic_id; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) handled |= handle_one_vic(&vic_devices[i], regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } while (handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct irq_domain_ops vic_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .map = vic_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * vic_register() - Register a VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @base: The base address of the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @parent_irq: The parent IRQ if cascaded, else 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @irq: The base IRQ for the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @valid_sources: bitmask of valid interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @resume_sources: bitmask of interrupts allowed for resume sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @node: The device tree node associated with the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Register the VIC with the system device tree so that it can be notified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * of suspend and resume requests and ensure that the correct actions are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * taken to re-instate the settings on resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * This also configures the IRQ domain for the VIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __init vic_register(void __iomem *base, unsigned int parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 valid_sources, u32 resume_sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct vic_device *v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (vic_id >= ARRAY_SIZE(vic_devices)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) v = &vic_devices[vic_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) v->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) v->valid_sources = valid_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) v->resume_sources = resume_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) set_handle_irq(vic_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) vic_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) vic_handle_irq_cascaded, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) &vic_irqdomain_ops, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* create an IRQ mapping for each valid IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (i = 0; i < fls(valid_sources); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (valid_sources & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) irq_create_mapping(v->domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* If no base IRQ was passed, figure out our allocated base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) v->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) v->irq = irq_find_mapping(v->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void vic_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *base = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int irq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* moreover, clear the soft-triggered, in case it was the reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void vic_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void __iomem *base = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int irq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void vic_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void __iomem *base = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int irq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel(1 << irq, base + VIC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #if defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct vic_device *vic_from_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct vic_device *v = vic_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int base_irq = irq & ~31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (id = 0; id < vic_id; id++, v++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (v->irq == base_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int vic_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct vic_device *v = vic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int off = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 bit = 1 << off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!(bit & v->resume_sources))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) v->resume_irqs |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) v->resume_irqs &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define vic_set_wake NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct irq_chip vic_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "VIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .irq_ack = vic_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .irq_mask = vic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .irq_unmask = vic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .irq_set_wake = vic_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void __init vic_disable(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(0, base + VIC_INT_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(0, base + VIC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(~0, base + VIC_INT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(0, base + VIC_ITCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(~0, base + VIC_INT_SOFT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void __init vic_clear_interrupts(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(0, base + VIC_PL190_VECT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < 19; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) value = readl(base + VIC_PL190_VECT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) writel(value, base + VIC_PL190_VECT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * The original cell has 32 interrupts, while the modified one has 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * the probe function is called twice, with base set to offset 000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * and 020 within the page. We call this "second block".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 vic_sources, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Disable all interrupts initially. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) vic_disable(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Make sure we clear all existing interrupts. The vector registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * in this cell are after the second block of general registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * so we can address them using standard offsets, but only from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * the second base address, which is 0x20 in the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (vic_2nd_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) vic_clear_interrupts(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* ST has 16 vectors as well, but we don't enable them by now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel(32, base + VIC_PL190_DEF_VECT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) vic_register(base, 0, irq_start, vic_sources, 0, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 vic_sources, u32 resume_sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 cellid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) enum amba_vendor vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Identify which VIC cell this one is, by reading the ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cellid |= (readl(addr) & 0xff) << (8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) vendor = (cellid >> 12) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) base, cellid, vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) switch(vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case AMBA_VENDOR_ST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) vic_init_st(base, irq_start, vic_sources, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case AMBA_VENDOR_ARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Disable all interrupts initially. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) vic_disable(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Make sure we clear all existing interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) vic_clear_interrupts(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) vic_init2(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * vic_init() - initialise a vectored interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @base: iomem base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @irq_start: starting interrupt number, must be muliple of 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @vic_sources: bitmask of interrupt sources to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @resume_sources: bitmask of interrupt sources to allow for resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) void __init vic_init(void __iomem *base, unsigned int irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 vic_sources, u32 resume_sources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int __init vic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 interrupt_mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 wakeup_mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) regs = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (WARN_ON(!regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) of_property_read_u32(node, "valid-mask", &interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) parent_irq = of_irq_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (parent_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) parent_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Passing 0 as first IRQ makes the simple domain allocate descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #endif /* CONFIG OF */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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