^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2015 Toradex AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Stefan Agner <stefan@agner.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The interrupt router is between the CPU's interrupt controller and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * peripheral. The router allows to route the peripheral interrupts to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Cortex-M4). The router will be configured transparently on a IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * o All peripheral interrupts of the Vybrid SoC can be routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * CPU 0, CPU 1 or both. The routing is useful for dual-core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * variants of Vybrid SoC such as VF6xx. This driver routes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * requested interrupt to the CPU currently running on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * o It is required to setup the interrupt router even on single-core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * variants of Vybrid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSCM_CPxNUM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSCM_IRSPRC(n) (0x80 + 2 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSCM_IRSPRC_CPEN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSCM_IRSPRC_NUM 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct vf610_mscm_ir_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *mscm_ir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 saved_irsprc[MSCM_IRSPRC_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool is_nvic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct vf610_mscm_ir_chip_data *mscm_ir_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) for (i = 0; i < MSCM_IRSPRC_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (i = 0; i < MSCM_IRSPRC_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int vf610_mscm_ir_notifier(struct notifier_block *self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) vf610_mscm_ir_save(mscm_ir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) vf610_mscm_ir_restore(mscm_ir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct notifier_block mscm_ir_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .notifier_call = vf610_mscm_ir_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void vf610_mscm_ir_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq_hw_number_t hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 irsprc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irsprc &= MSCM_IRSPRC_CPEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) WARN_ON(irsprc & ~chip_data->cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writew_relaxed(chip_data->cpu_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) irq_chip_enable_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void vf610_mscm_ir_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq_hw_number_t hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) irq_chip_disable_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct irq_chip vf610_mscm_ir_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "mscm-ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irq_enable = vf610_mscm_ir_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .irq_disable = vf610_mscm_ir_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!irq_domain_get_of_node(domain->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &vf610_mscm_ir_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (mscm_ir_data->is_nvic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) parent_fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) parent_fwspec.param[0] = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) parent_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) parent_fwspec.param[0] = GIC_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) parent_fwspec.param[1] = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) parent_fwspec.param[2] = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int vf610_mscm_ir_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (WARN_ON(fwspec->param_count < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct irq_domain_ops mscm_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .translate = vf610_mscm_ir_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .alloc = vf610_mscm_ir_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int __init vf610_mscm_ir_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct irq_domain *domain, *domain_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct regmap *mscm_cp_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret, cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) domain_parent = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!domain_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pr_err("vf610_mscm_ir: interrupt-parent not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!mscm_ir_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ERR(mscm_ir_data->mscm_ir_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_err("vf610_mscm_ir: unable to map mscm register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = PTR_ERR(mscm_ir_data->mscm_ir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (IS_ERR(mscm_cp_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = PTR_ERR(mscm_cp_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mscm_ir_data->cpu_mask = 0x1 << cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) domain = irq_domain_add_hierarchy(domain_parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MSCM_IRSPRC_NUM, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &mscm_irq_domain_ops, mscm_ir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (of_device_is_compatible(irq_domain_get_of_node(domain->parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "arm,armv7m-nvic"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mscm_ir_data->is_nvic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cpu_pm_register_notifier(&mscm_ir_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) iounmap(mscm_ir_data->mscm_ir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree(mscm_ir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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