Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for UniPhier AIDET (ARM Interrupt Detector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define UNIPHIER_AIDET_NR_IRQS		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UNIPHIER_AIDET_DETCONF		0x04	/* inverter register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct uniphier_aidet_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 saved_vals[UNIPHIER_AIDET_NR_IRQS / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static void uniphier_aidet_reg_update(struct uniphier_aidet_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 				      unsigned int reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	tmp = readl_relaxed(priv->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	tmp |= mask & val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	writel_relaxed(tmp, priv->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void uniphier_aidet_detconf_update(struct uniphier_aidet_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					  unsigned long index, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	reg = UNIPHIER_AIDET_DETCONF + index / 32 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mask = BIT(index % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int uniphier_aidet_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct uniphier_aidet_priv *priv = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* enable inverter for active low triggers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	uniphier_aidet_detconf_update(priv, data->hwirq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return irq_chip_set_type_parent(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct irq_chip uniphier_aidet_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.name = "AIDET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.irq_set_type = uniphier_aidet_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int uniphier_aidet_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					   struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 					   unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 					   unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (WARN_ON(fwspec->param_count < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	*out_hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int uniphier_aidet_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				       unsigned int virq, unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				       void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (nr_irqs != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ret = uniphier_aidet_domain_translate(domain, arg, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (hwirq >= UNIPHIER_AIDET_NR_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 					    &uniphier_aidet_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 					    domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* parent is GIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	parent_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	parent_fwspec.param[0] = 0;		/* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	parent_fwspec.param[1] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	parent_fwspec.param[2] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct irq_domain_ops uniphier_aidet_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.alloc = uniphier_aidet_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.translate = uniphier_aidet_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int uniphier_aidet_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct device_node *parent_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct uniphier_aidet_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	parent_np = of_irq_find_parent(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (!parent_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	parent_domain = irq_find_host(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	of_node_put(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (IS_ERR(priv->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return PTR_ERR(priv->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	priv->domain = irq_domain_create_hierarchy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					UNIPHIER_AIDET_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					of_node_to_fwnode(dev->of_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					&uniphier_aidet_domain_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (!priv->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int __maybe_unused uniphier_aidet_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		priv->saved_vals[i] = readl_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __maybe_unused uniphier_aidet_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		writel_relaxed(priv->saved_vals[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			       priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct dev_pm_ops uniphier_aidet_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(uniphier_aidet_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				      uniphier_aidet_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id uniphier_aidet_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "socionext,uniphier-ld4-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ .compatible = "socionext,uniphier-pro4-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ .compatible = "socionext,uniphier-sld8-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{ .compatible = "socionext,uniphier-pro5-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{ .compatible = "socionext,uniphier-pxs2-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	{ .compatible = "socionext,uniphier-ld11-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	{ .compatible = "socionext,uniphier-ld20-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	{ .compatible = "socionext,uniphier-pxs3-aidet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct platform_driver uniphier_aidet_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.probe = uniphier_aidet_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.name = "uniphier-aidet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.of_match_table = uniphier_aidet_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.pm = &uniphier_aidet_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) builtin_platform_driver(uniphier_aidet_driver);