^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Texas Instruments' K3 Interrupt Aggregator irqchip driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Lokesh Vutla <lokeshvutla@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/soc/ti/ti_sci_inta_msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/soc/ti/ti_sci_protocol.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm-generic/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TI_SCI_DEV_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TI_SCI_DEV_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TI_SCI_IRQ_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TI_SCI_IRQ_ID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (TI_SCI_DEV_ID_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TO_HWIRQ(dev, index) ((((dev) & TI_SCI_DEV_ID_MASK) << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) TI_SCI_DEV_ID_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ((index) & TI_SCI_IRQ_ID_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX_EVENTS_PER_VINT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VINT_ENABLE_SET_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VINT_ENABLE_CLR_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VINT_STATUS_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VINT_STATUS_MASKED_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * struct ti_sci_inta_event_desc - Description of an event coming to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Interrupt Aggregator. This serves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * as a mapping table for global event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * hwirq and vint bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @global_event: Global event number corresponding to this event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @hwirq: Hwirq of the incoming interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @vint_bit: Corresponding vint bit to which this event is attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ti_sci_inta_event_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 global_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 vint_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * of Interrupt Aggregator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @domain: Pointer to IRQ domain to which this vint belongs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @list: List entry for the vint list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @event_map: Bitmap to manage the allocation of events to vint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @events: Array of event descriptors assigned to this vint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @parent_virq: Linux IRQ number that gets attached to parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @vint_id: TISCI vint ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ti_sci_inta_vint_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DECLARE_BITMAP(event_map, MAX_EVENTS_PER_VINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct ti_sci_inta_event_desc events[MAX_EVENTS_PER_VINT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int parent_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 vint_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * struct ti_sci_inta_irq_domain - Structure representing a TISCI based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Interrupt Aggregator IRQ domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @sci: Pointer to TISCI handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @vint: TISCI resource pointer representing IA inerrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @global_event: TISCI resource pointer representing global events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @vint_list: List of the vints active in the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @vint_mutex: Mutex to protect vint_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @base: Base address of the memory mapped IO registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @pdev: Pointer to platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ti_sci_id: TI-SCI device identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @unmapped_cnt: Number of @unmapped_dev_ids entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @unmapped_dev_ids: Pointer to an array of TI-SCI device identifiers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * unmapped event sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Unmapped Events are not part of the Global Event Map and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * they are converted to Global event within INTA to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * received by the same INTA to generate an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * In case an interrupt request comes for a device which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * generating Unmapped Event, we must use the INTA's TI-SCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * device identifier in place of the source device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * identifier to let sysfw know where it has to program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Global Event number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct ti_sci_inta_irq_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct ti_sci_handle *sci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct ti_sci_resource *vint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ti_sci_resource *global_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct list_head vint_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Mutex to protect vint list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct mutex vint_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 ti_sci_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int unmapped_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 *unmapped_dev_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) events[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, u32 hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 dev_id = HWIRQ_TO_DEVID(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (inta->unmapped_cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * For devices sending Unmapped Events we must use the INTA's TI-SCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * device identifier number to be able to convert it to a Global Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * and map it to an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = 0; i < inta->unmapped_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (dev_id == inta->unmapped_dev_ids[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_id = inta->ti_sci_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * ti_sci_inta_irq_handler() - Chained IRQ handler for the vint irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @desc: Pointer to irq_desc corresponding to the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void ti_sci_inta_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct ti_sci_inta_vint_desc *vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ti_sci_inta_irq_domain *inta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int virq, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) vint_desc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) domain = vint_desc->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) inta = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) chained_irq_enter(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) VINT_STATUS_MASKED_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for_each_set_bit(bit, &val, MAX_EVENTS_PER_VINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) virq = irq_find_mapping(domain, vint_desc->events[bit].hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) chained_irq_exit(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @inta: IRQ domain corresponding to Interrupt Aggregator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @irq: Hardware irq corresponding to the above irq domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Return parent irq number if translation is available else -ENOENT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int ti_sci_inta_xlate_irq(struct ti_sci_inta_irq_domain *inta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 vint_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct device_node *np = dev_of_node(&inta->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 base, parent_base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const __be32 *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) range = of_get_property(np, "ti,interrupt-ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return vint_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (len /= sizeof(*range); len >= 3; len -= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) base = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) parent_base = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) size = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (base <= vint_id && vint_id < base + size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return vint_id - base + parent_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * ti_sci_inta_alloc_parent_irq() - Allocate parent irq to Interrupt aggregator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @domain: IRQ domain corresponding to Interrupt Aggregator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Return 0 if all went well else corresponding error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ti_sci_inta_irq_domain *inta = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct ti_sci_inta_vint_desc *vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct device_node *parent_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int parent_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int p_hwirq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 vint_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) vint_id = ti_sci_get_free_resource(inta->vint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (vint_id == TI_SCI_RESOURCE_NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) p_hwirq = ti_sci_inta_xlate_irq(inta, vint_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (p_hwirq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = p_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto free_vint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vint_desc = kzalloc(sizeof(*vint_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!vint_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto free_vint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) vint_desc->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) vint_desc->vint_id = vint_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) INIT_LIST_HEAD(&vint_desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) parent_node = of_irq_find_parent(dev_of_node(&inta->pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) parent_fwspec.fwnode = of_node_to_fwnode(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Parent is GIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) parent_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) parent_fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) parent_fwspec.param[1] = p_hwirq - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) parent_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Parent is Interrupt Router */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) parent_fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) parent_fwspec.param[0] = p_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) parent_virq = irq_create_fwspec_mapping(&parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (parent_virq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(&inta->pdev->dev, "Parent IRQ allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto free_vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) vint_desc->parent_virq = parent_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) list_add_tail(&vint_desc->list, &inta->vint_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_set_chained_handler_and_data(vint_desc->parent_virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ti_sci_inta_irq_handler, vint_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) free_vint_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) kfree(vint_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) free_vint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ti_sci_release_resource(inta->vint, vint_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * ti_sci_inta_alloc_event() - Attach an event to a IA vint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @vint_desc: Pointer to vint_desc to which the event gets attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @free_bit: Bit inside vint to which event gets attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @hwirq: hwirq of the input event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Return event_desc pointer if all went ok else appropriate error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_event(struct ti_sci_inta_vint_desc *vint_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 free_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ti_sci_inta_irq_domain *inta = vint_desc->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ti_sci_inta_event_desc *event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u16 dev_id, dev_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_id = ti_sci_inta_get_dev_id(inta, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_index = HWIRQ_TO_IRQID(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) event_desc = &vint_desc->events[free_bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) event_desc->hwirq = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) event_desc->vint_bit = free_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) event_desc->global_event = ti_sci_get_free_resource(inta->global_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (event_desc->global_event == TI_SCI_RESOURCE_NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) err = inta->sci->ops.rm_irq_ops.set_event_map(inta->sci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_id, dev_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) inta->ti_sci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vint_desc->vint_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) event_desc->global_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) free_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto free_global_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) free_global_event:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ti_sci_release_resource(inta->global_event, event_desc->global_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * ti_sci_inta_alloc_irq() - Allocate an irq within INTA domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @domain: irq_domain pointer corresponding to INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @hwirq: hwirq of the input event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Note: Allocation happens in the following manner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * - Find a free bit available in any of the vints available in the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * - If not found, allocate a vint from the vint pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * - Attach the free bit to input hwirq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Return event_desc if all went ok else appropriate error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_irq(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct ti_sci_inta_irq_domain *inta = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct ti_sci_inta_vint_desc *vint_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct ti_sci_inta_event_desc *event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 free_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_lock(&inta->vint_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) list_for_each_entry(vint_desc, &inta->vint_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) free_bit = find_first_zero_bit(vint_desc->event_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MAX_EVENTS_PER_VINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (free_bit != MAX_EVENTS_PER_VINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) set_bit(free_bit, vint_desc->event_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto alloc_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* No free bits available. Allocate a new vint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vint_desc = ti_sci_inta_alloc_parent_irq(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (IS_ERR(vint_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) event_desc = ERR_CAST(vint_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) free_bit = find_first_zero_bit(vint_desc->event_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MAX_EVENTS_PER_VINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) set_bit(free_bit, vint_desc->event_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) alloc_event:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) event_desc = ti_sci_inta_alloc_event(vint_desc, free_bit, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (IS_ERR(event_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clear_bit(free_bit, vint_desc->event_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mutex_unlock(&inta->vint_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * ti_sci_inta_free_parent_irq() - Free a parent irq to INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @inta: Pointer to inta domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @vint_desc: Pointer to vint_desc that needs to be freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void ti_sci_inta_free_parent_irq(struct ti_sci_inta_irq_domain *inta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct ti_sci_inta_vint_desc *vint_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (find_first_bit(vint_desc->event_map, MAX_EVENTS_PER_VINT) == MAX_EVENTS_PER_VINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) list_del(&vint_desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ti_sci_release_resource(inta->vint, vint_desc->vint_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) irq_dispose_mapping(vint_desc->parent_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) kfree(vint_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * ti_sci_inta_free_irq() - Free an IRQ within INTA domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @event_desc: Pointer to event_desc that needs to be freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @hwirq: Hwirq number within INTA domain that needs to be freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void ti_sci_inta_free_irq(struct ti_sci_inta_event_desc *event_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct ti_sci_inta_vint_desc *vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ti_sci_inta_irq_domain *inta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u16 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) vint_desc = to_vint_desc(event_desc, event_desc->vint_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) inta = vint_desc->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_id = ti_sci_inta_get_dev_id(inta, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* free event irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mutex_lock(&inta->vint_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_id, HWIRQ_TO_IRQID(hwirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) inta->ti_sci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) vint_desc->vint_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) event_desc->global_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) event_desc->vint_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clear_bit(event_desc->vint_bit, vint_desc->event_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ti_sci_release_resource(inta->global_event, event_desc->global_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) event_desc->global_event = TI_SCI_RESOURCE_NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) event_desc->hwirq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ti_sci_inta_free_parent_irq(inta, vint_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mutex_unlock(&inta->vint_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * ti_sci_inta_request_resources() - Allocate resources for input irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Note: This is the core api where the actual allocation happens for input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * hwirq. This allocation involves creating a parent irq for vint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * If this is done in irq_domain_ops.alloc() then a deadlock is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * for allocation. So this allocation is being done in request_resources()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Return: 0 if all went well else corresponding error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int ti_sci_inta_request_resources(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct ti_sci_inta_event_desc *event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) event_desc = ti_sci_inta_alloc_irq(data->domain, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (IS_ERR(event_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return PTR_ERR(event_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) data->chip_data = event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * ti_sci_inta_release_resources - Release resources for input irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Note: Corresponding to request_resources(), all the unmapping and deletion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * of parent vint irqs happens in this api.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void ti_sci_inta_release_resources(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct ti_sci_inta_event_desc *event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) event_desc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ti_sci_inta_free_irq(event_desc, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * ti_sci_inta_manage_event() - Control the event based on the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * @offset: register offset using which event is controlled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void ti_sci_inta_manage_event(struct irq_data *data, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct ti_sci_inta_event_desc *event_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ti_sci_inta_vint_desc *vint_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct ti_sci_inta_irq_domain *inta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) event_desc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) vint_desc = to_vint_desc(event_desc, event_desc->vint_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) inta = data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writeq_relaxed(BIT(event_desc->vint_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) inta->base + vint_desc->vint_id * 0x1000 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * ti_sci_inta_mask_irq() - Mask an event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void ti_sci_inta_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ti_sci_inta_manage_event(data, VINT_ENABLE_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * ti_sci_inta_unmask_irq() - Unmask an event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void ti_sci_inta_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ti_sci_inta_manage_event(data, VINT_ENABLE_SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * ti_sci_inta_ack_irq() - Ack an event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void ti_sci_inta_ack_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Do not clear the event if hardware is capable of sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * a down event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (irqd_get_trigger_type(data) != IRQF_TRIGGER_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ti_sci_inta_manage_event(data, VINT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int ti_sci_inta_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) const struct cpumask *mask_val, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * ti_sci_inta_set_type() - Update the trigger type of the irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * @data: Pointer to corresponding irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * @type: Trigger type as specified by user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Note: This updates the handle_irq callback for level msi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Return 0 if all went well else appropriate error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int ti_sci_inta_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * .alloc default sets handle_edge_irq. But if the user specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * that IRQ is level MSI, then update the handle to handle_level_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case IRQF_TRIGGER_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case IRQF_TRIGGER_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct irq_chip ti_sci_inta_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "INTA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .irq_ack = ti_sci_inta_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .irq_mask = ti_sci_inta_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .irq_set_type = ti_sci_inta_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .irq_unmask = ti_sci_inta_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .irq_set_affinity = ti_sci_inta_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .irq_request_resources = ti_sci_inta_request_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .irq_release_resources = ti_sci_inta_release_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * ti_sci_inta_irq_domain_free() - Free an IRQ from the IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @domain: Domain to which the irqs belong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @virq: base linux virtual IRQ to be freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @nr_irqs: Number of continuous irqs to be freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void ti_sci_inta_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct irq_data *data = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) irq_domain_reset_irq_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * ti_sci_inta_irq_domain_alloc() - Allocate Interrupt aggregator IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @domain: Point to the interrupt aggregator IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * @virq: Corresponding Linux virtual IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * @nr_irqs: Continuous irqs to be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * @data: Pointer to firmware specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * No actual allocation happens here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Return 0 if all went well else appropriate error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int ti_sci_inta_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int virq, unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msi_alloc_info_t *arg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) irq_domain_set_info(domain, virq, arg->hwirq, &ti_sci_inta_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) NULL, handle_edge_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct irq_domain_ops ti_sci_inta_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .free = ti_sci_inta_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .alloc = ti_sci_inta_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static struct irq_chip ti_sci_inta_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "MSI-INTA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .flags = IRQCHIP_SUPPORTS_LEVEL_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void ti_sci_inta_msi_set_desc(msi_alloc_info_t *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct platform_device *pdev = to_platform_device(desc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) arg->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) arg->hwirq = TO_HWIRQ(pdev->id, desc->inta.dev_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct msi_domain_ops ti_sci_inta_msi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .set_desc = ti_sci_inta_msi_set_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct msi_domain_info ti_sci_inta_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MSI_FLAG_LEVEL_CAPABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &ti_sci_inta_msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .chip = &ti_sci_inta_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int ti_sci_inta_get_unmapped_sources(struct ti_sci_inta_irq_domain *inta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct device *dev = &inta->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct device_node *node = dev_of_node(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct of_phandle_iterator it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int count, err, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) count = of_count_phandle_with_args(node, "ti,unmapped-event-sources", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) inta->unmapped_dev_ids = devm_kcalloc(dev, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sizeof(*inta->unmapped_dev_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!inta->unmapped_dev_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) of_for_each_phandle(&it, err, node, "ti,unmapped-event-sources", NULL, 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = of_property_read_u32(it.node, "ti,sci-dev-id", &dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(dev, "ti,sci-dev-id read failure for %pOFf\n", it.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) of_node_put(it.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) inta->unmapped_dev_ids[i++] = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) inta->unmapped_cnt = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct irq_domain *parent_domain, *domain, *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct device_node *parent_node, *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct ti_sci_inta_irq_domain *inta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) node = dev_of_node(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) parent_node = of_irq_find_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!parent_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_err(dev, "Failed to get IRQ parent node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) parent_domain = irq_find_host(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) inta = devm_kzalloc(dev, sizeof(*inta), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!inta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) inta->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) inta->sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (IS_ERR(inta->sci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return dev_err_probe(dev, PTR_ERR(inta->sci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "ti,sci read fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", &inta->ti_sci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(dev, "missing 'ti,sci-dev-id' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) inta->vint = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) TI_SCI_RESASG_SUBTYPE_IA_VINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (IS_ERR(inta->vint)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_err(dev, "VINT resource allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return PTR_ERR(inta->vint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) inta->global_event = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (IS_ERR(inta->global_event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(dev, "Global event resource allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return PTR_ERR(inta->global_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) inta->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (IS_ERR(inta->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return PTR_ERR(inta->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = ti_sci_inta_get_unmapped_sources(inta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) domain = irq_domain_add_linear(dev_of_node(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ti_sci_get_num_resources(inta->vint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &ti_sci_inta_irq_domain_ops, inta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(dev, "Failed to allocate IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) msi_domain = ti_sci_inta_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &ti_sci_inta_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(dev, "Failed to allocate msi domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) INIT_LIST_HEAD(&inta->vint_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mutex_init(&inta->vint_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_info(dev, "Interrupt Aggregator domain %d created\n", inta->ti_sci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const struct of_device_id ti_sci_inta_irq_domain_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { .compatible = "ti,sci-inta", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MODULE_DEVICE_TABLE(of, ti_sci_inta_irq_domain_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct platform_driver ti_sci_inta_irq_domain_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .probe = ti_sci_inta_irq_domain_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "ti-sci-inta",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .of_match_table = ti_sci_inta_irq_domain_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) module_platform_driver(ti_sci_inta_irq_domain_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_AUTHOR("Lokesh Vutla <lokeshvutla@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("K3 Interrupt Aggregator driver over TI SCI protocol");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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