Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver code for Tegra's Legacy Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Heavily based on the original arch/arm/mach-tegra/irq.c code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2010,2013, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ICTLR_CPU_IEP_VFIQ	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ICTLR_CPU_IEP_FIR	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ICTLR_CPU_IEP_FIR_SET	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ICTLR_CPU_IEP_FIR_CLR	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ICTLR_CPU_IER		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ICTLR_CPU_IER_SET	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ICTLR_CPU_IER_CLR	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ICTLR_CPU_IEP_CLASS	0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ICTLR_COP_IER		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ICTLR_COP_IER_SET	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ICTLR_COP_IER_CLR	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ICTLR_COP_IEP_CLASS	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA_MAX_NUM_ICTLRS	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static unsigned int num_ictlrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct tegra_ictlr_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int num_ictlrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.num_ictlrs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.num_ictlrs = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.num_ictlrs = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct of_device_id ictlr_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct tegra_ictlr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct tegra_ictlr_info *lic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	void __iomem *base = (void __iomem __force *)d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mask = BIT(d->hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	writel_relaxed(mask, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void tegra_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void tegra_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void tegra_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int tegra_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return irq_chip_retrigger_hierarchy(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int tegra_set_wake(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 irq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 index, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	index = (irq / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mask = BIT(irq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		lic->ictlr_wake_mask[index] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		lic->ictlr_wake_mask[index] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Do *not* call into the parent, as the GIC doesn't have any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * wake-up facility...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int tegra_ictlr_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	for (i = 0; i < num_ictlrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		void __iomem *ictlr = lic->base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		/* Save interrupt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/* Disable COP interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		/* Disable CPU interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* Enable the wakeup sources of ictlr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void tegra_ictlr_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	for (i = 0; i < num_ictlrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		void __iomem *ictlr = lic->base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		writel_relaxed(lic->cpu_iep[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			       ictlr + ICTLR_CPU_IEP_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		writel_relaxed(lic->cpu_ier[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			       ictlr + ICTLR_CPU_IER_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		writel_relaxed(lic->cop_iep[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			       ictlr + ICTLR_COP_IEP_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		writel_relaxed(lic->cop_ier[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			       ictlr + ICTLR_COP_IER_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct syscore_ops tegra_ictlr_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.suspend	= tegra_ictlr_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.resume		= tegra_ictlr_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void tegra_ictlr_syscore_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	register_syscore_ops(&tegra_ictlr_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define tegra_set_wake	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void tegra_ictlr_syscore_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct irq_chip tegra_ictlr_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.name			= "LIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.irq_eoi		= tegra_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.irq_mask		= tegra_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.irq_unmask		= tegra_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.irq_retrigger		= tegra_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.irq_set_wake		= tegra_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.irq_set_type		= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.flags			= IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int tegra_ictlr_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 					struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 					unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		/* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		*hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				    unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				    unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct tegra_ictlr_info *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -EINVAL;	/* Not GIC compliant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (fwspec->param[0] != GIC_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EINVAL;	/* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (hwirq >= (num_ictlrs * 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		int ictlr = (hwirq + i) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 					      &tegra_ictlr_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					      (void __force *)info->base[ictlr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	parent_fwspec = *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					    &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct irq_domain_ops tegra_ictlr_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.translate	= tegra_ictlr_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.alloc		= tegra_ictlr_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.free		= irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int __init tegra_ictlr_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				   struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct irq_domain *parent_domain, *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	const struct tegra_ictlr_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		pr_err("%pOF: no parent, giving up\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		pr_err("%pOF: unable to obtain parent domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	match = of_match_node(ictlr_matches, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!match)		/* Should never happen... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	soc = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	lic = kzalloc(sizeof(*lic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!lic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		base = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		lic->base[i] = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		/* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		/* All interrupts target IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		num_ictlrs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!num_ictlrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		pr_err("%pOF: no valid regions, giving up\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	WARN(num_ictlrs != soc->num_ictlrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	     "%pOF: Found %u interrupt controllers in DT; expected %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	     node, num_ictlrs, soc->num_ictlrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 					  node, &tegra_ictlr_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					  lic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		pr_err("%pOF: failed to allocated domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	tegra_ictlr_syscore_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pr_info("%pOF: %d interrupts forwarded to %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		node, num_ictlrs * 32, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	for (i = 0; i < num_ictlrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		iounmap(lic->base[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	kfree(lic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);