Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Mans Rullgard <mans@mansr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IRQ0_CTL_BASE		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IRQ1_CTL_BASE		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define EDGE_CTL_BASE		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IRQ2_CTL_BASE		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IRQ_CTL_HI		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define EDGE_CTL_HI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IRQ_STATUS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IRQ_RAWSTAT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IRQ_EN_SET		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IRQ_EN_CLR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IRQ_SOFT_SET		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IRQ_SOFT_CLR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define EDGE_STATUS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define EDGE_RAWSTAT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define EDGE_CFG_RISE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EDGE_CFG_FALL		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EDGE_CFG_RISE_SET	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EDGE_CFG_RISE_CLR	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EDGE_CFG_FALL_SET	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EDGE_CFG_FALL_CLR	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct tangox_irq_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned long ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static inline u32 intc_readl(struct tangox_irq_chip *chip, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return readl_relaxed(chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static inline void intc_writel(struct tangox_irq_chip *chip, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	writel_relaxed(val, chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void tangox_dispatch_irqs(struct irq_domain *dom, unsigned int status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				 int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		hwirq = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		virq = irq_find_mapping(dom, base + hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		status &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void tangox_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct irq_domain *dom = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct tangox_irq_chip *chip = dom->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned int status_lo, status_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	chained_irq_enter(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	tangox_dispatch_irqs(dom, status_lo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	tangox_dispatch_irqs(dom, status_hi, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	chained_irq_exit(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int tangox_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct tangox_irq_chip *chip = gc->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct irq_chip_regs *regs = &gc->chip_types[0].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	switch (flow_type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		pr_err("Invalid trigger mode %x for IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		       flow_type, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return irq_setup_alt_chip(d, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void __init tangox_irq_init_chip(struct irq_chip_generic *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					unsigned long ctl_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 					unsigned long edge_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct tangox_irq_chip *chip = gc->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long ctl_base = chip->ctl + ctl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned long edge_base = EDGE_CTL_BASE + edge_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	gc->reg_base = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	gc->unused = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		ct[i].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		ct[i].chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		ct[i].chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		ct[i].chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		ct[i].chip.irq_set_type = tangox_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		ct[i].chip.name = gc->domain->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ct[i].regs.enable = ctl_base + IRQ_EN_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		ct[i].regs.disable = ctl_base + IRQ_EN_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		ct[i].regs.ack = edge_base + EDGE_RAWSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ct[i].regs.type = edge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ct[0].type = IRQ_TYPE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ct[0].handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ct[1].type = IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ct[1].handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	intc_writel(chip, ct->regs.disable, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	intc_writel(chip, ct->regs.ack, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void __init tangox_irq_domain_init(struct irq_domain *dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		gc = irq_get_domain_generic_chip(dom, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		tangox_irq_init_chip(gc, i * IRQ_CTL_HI, i * EDGE_CTL_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int __init tangox_irq_init(void __iomem *base, struct resource *baseres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				  struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct tangox_irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct irq_domain *dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		panic("%pOFn: failed to get IRQ", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	err = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		panic("%pOFn: failed to get address", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	chip->ctl = res.start - baseres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	chip->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	dom = irq_domain_add_linear(node, 64, &irq_generic_chip_ops, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (!dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		panic("%pOFn: failed to create irqdomain", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	err = irq_alloc_domain_generic_chips(dom, 32, 2, node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					     handle_level_irq, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		panic("%pOFn: failed to allocate irqchip", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	tangox_irq_domain_init(dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	irq_set_chained_handler_and_data(irq, tangox_irq_handler, dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int __init tangox_of_irq_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				     struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct device_node *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		panic("%pOFn: of_iomap failed", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	for_each_child_of_node(node, c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		tangox_irq_init(base, &res, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IRQCHIP_DECLARE(tangox_intc, "sigma,smp8642-intc", tangox_of_irq_init);