^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner A1X SoCs IRQ chip driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benn Huang <benn@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUN4I_IRQ_VECTOR_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN4I_IRQ_PROTECTION_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN4I_IRQ_NMI_CTRL_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN4I_IRQ_MASK_REG_OFFSET 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUNIV_IRQ_MASK_REG_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sun4i_irq_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 enable_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 mask_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct sun4i_irq_chip_data *irq_ic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void sun4i_irq_ack(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int irq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (irq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return; /* Only IRQ 0 / the ENMI needs to be acked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void sun4i_irq_mask(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int irq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int irq_off = irq % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int reg = irq / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val = readl(irq_ic_data->irq_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(val & ~(1 << irq_off),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void sun4i_irq_unmask(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int irq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int irq_off = irq % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int reg = irq / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val = readl(irq_ic_data->irq_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(val | (1 << irq_off),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct irq_chip sun4i_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "sun4i_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .irq_eoi = sun4i_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_mask = sun4i_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .irq_unmask = sun4i_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) irq_set_probe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct irq_domain_ops sun4i_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .map = sun4i_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int __init sun4i_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) irq_ic_data->irq_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!irq_ic_data->irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) panic("%pOF: unable to map IC registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Clear all the pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Enable protection mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Configure the external interrupt source type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &sun4i_irq_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!irq_ic_data->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) panic("%pOF: unable to create IRQ domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) set_handle_irq(sun4i_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int __init sun4i_ic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!irq_ic_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_err("kzalloc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return sun4i_of_init(node, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int __init suniv_ic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!irq_ic_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_err("kzalloc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return sun4i_of_init(node, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) suniv_ic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * hwirq == 0 can mean one of 3 things:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * 1) no more irqs pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * 2) irq 0 pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * 3) spurious irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * So if we immediately get a reading of 0, check the irq-pending reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * to differentiate between 2 and 3. We only do this once to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * the extra check in the common case of 1 hapening after having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * read the vector-reg once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (hwirq == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BIT(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hwirq = readl(irq_ic_data->irq_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SUN4I_IRQ_VECTOR_REG) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } while (hwirq != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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