^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Maxime Coquelin 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQS_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HWSPNLCK_TIMEOUT 1000 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct stm32_exti_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 imr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 emr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 rtsr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 ftsr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 swier_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 rpr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 fpr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UNDEF_REG ~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct stm32_desc_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 exti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct stm32_exti_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct stm32_exti_bank **exti_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct stm32_desc_irq *desc_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 bank_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 irq_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct stm32_exti_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct stm32_exti_host_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct stm32_exti_bank *reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct raw_spinlock rlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 wake_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 mask_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 rtsr_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 ftsr_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct stm32_exti_host_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct stm32_exti_chip_data *chips_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct stm32_exti_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct stm32_exti_host_data *stm32_host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .imr_ofst = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .emr_ofst = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .rtsr_ofst = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ftsr_ofst = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .swier_ofst = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .rpr_ofst = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .fpr_ofst = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &stm32f4xx_exti_b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .exti_banks = stm32f4xx_exti_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .imr_ofst = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .emr_ofst = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .rtsr_ofst = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .ftsr_ofst = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .swier_ofst = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .rpr_ofst = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .fpr_ofst = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .imr_ofst = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .emr_ofst = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rtsr_ofst = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .ftsr_ofst = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .swier_ofst = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .rpr_ofst = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .fpr_ofst = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .imr_ofst = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .emr_ofst = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .rtsr_ofst = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ftsr_ofst = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .swier_ofst = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .rpr_ofst = 0xA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .fpr_ofst = UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &stm32h7xx_exti_b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &stm32h7xx_exti_b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &stm32h7xx_exti_b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .exti_banks = stm32h7xx_exti_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct stm32_exti_bank stm32mp1_exti_b1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .imr_ofst = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .emr_ofst = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .rtsr_ofst = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .ftsr_ofst = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .swier_ofst = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .rpr_ofst = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .fpr_ofst = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct stm32_exti_bank stm32mp1_exti_b2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .imr_ofst = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .emr_ofst = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .rtsr_ofst = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .ftsr_ofst = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .swier_ofst = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .rpr_ofst = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .fpr_ofst = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct stm32_exti_bank stm32mp1_exti_b3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .imr_ofst = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .emr_ofst = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .rtsr_ofst = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .ftsr_ofst = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .swier_ofst = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .rpr_ofst = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .fpr_ofst = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &stm32mp1_exti_b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &stm32mp1_exti_b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &stm32mp1_exti_b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct irq_chip stm32_exti_h_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct irq_chip stm32_exti_h_chip_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct stm32_exti_drv_data stm32mp1_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .exti_banks = stm32mp1_exti_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .desc_irqs = stm32mp1_desc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct stm32_desc_irq *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!drv_data->desc_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) for (i = 0; i < drv_data->irq_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) desc = &drv_data->desc_irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (desc->exti == hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct stm32_exti_chip_data *chip_data = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (stm32_bank->fpr_ofst != UNDEF_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void stm32_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct irq_domain *domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int virq, nbanks = domain->gc->num_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int n, i, irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gc = irq_get_domain_generic_chip(domain, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) while ((pending = stm32_exti_pending(gc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for_each_set_bit(n, &pending, IRQS_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) virq = irq_find_mapping(domain, irq_base + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int stm32_exti_set_type(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int type, u32 *rtsr, u32 *ftsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *rtsr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *ftsr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *rtsr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *ftsr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *rtsr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *ftsr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct stm32_exti_chip_data *chip_data = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct hwspinlock *hwlock = chip_data->host_data->hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 rtsr, ftsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto unspinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unspinlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) hwspin_unlock_in_atomic(hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 wake_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* save rtsr, ftsr registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 mask_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* restore rtsr, ftsr, registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void stm32_irq_suspend(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct stm32_exti_chip_data *chip_data = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) stm32_chip_suspend(chip_data, gc->wake_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void stm32_irq_resume(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct stm32_exti_chip_data *chip_data = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) stm32_chip_resume(chip_data, gc->mask_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) irq_map_generic_chip(d, virq, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct irq_data *data = irq_domain_get_irq_data(d, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) irq_domain_reset_irq_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct irq_domain_ops irq_exti_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .map = irq_map_generic_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .alloc = stm32_exti_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .free = stm32_exti_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void stm32_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct stm32_exti_chip_data *chip_data = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (stm32_bank->fpr_ofst != UNDEF_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* directly set the target bit without reading first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 val = BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) val |= BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val = readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val &= ~BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void stm32_exti_h_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (stm32_bank->fpr_ofst != UNDEF_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (d->parent_data->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void stm32_exti_h_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (d->parent_data->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void stm32_exti_h_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (d->parent_data->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct hwspinlock *hwlock = chip_data->host_data->hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 rtsr, ftsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto unspinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unspinlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hwspin_unlock_in_atomic(hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) chip_data->wake_active |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) chip_data->wake_active &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int stm32_exti_h_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const struct cpumask *dest, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (d->parent_data->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return irq_chip_set_affinity_parent(d, dest, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int __maybe_unused stm32_exti_h_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct stm32_exti_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) chip_data = &stm32_host_data->chips_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) stm32_chip_suspend(chip_data, chip_data->wake_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void __maybe_unused stm32_exti_h_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct stm32_exti_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) chip_data = &stm32_host_data->chips_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) raw_spin_lock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) stm32_chip_resume(chip_data, chip_data->mask_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) raw_spin_unlock(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct syscore_ops stm32_exti_h_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .suspend = stm32_exti_h_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .resume = stm32_exti_h_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) stm32_host_data = host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) register_syscore_ops(&stm32_exti_h_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void stm32_exti_h_syscore_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unregister_syscore_ops(&stm32_exti_h_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int stm32_exti_h_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void __iomem *base = chip_data->host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) writel_relaxed(mask, base + stm32_bank->swier_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct irq_chip stm32_exti_h_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .name = "stm32-exti-h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .irq_eoi = stm32_exti_h_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .irq_mask = stm32_exti_h_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .irq_unmask = stm32_exti_h_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .irq_retrigger = stm32_exti_h_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .irq_set_type = stm32_exti_h_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .irq_set_wake = stm32_exti_h_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct irq_chip stm32_exti_h_chip_direct = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "stm32-exti-h-direct",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .irq_set_wake = stm32_exti_h_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct stm32_exti_host_data *host_data = dm->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct stm32_exti_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) const struct stm32_desc_irq *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct irq_fwspec p_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bank = hwirq / IRQS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) chip_data = &host_data->chips_data[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (desc->irq_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) p_fwspec.fwnode = dm->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) p_fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) p_fwspec.param[0] = GIC_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) p_fwspec.param[1] = desc->irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct stm32_exti_host_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!host_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) host_data->drv_data = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) host_data->chips_data = kcalloc(dd->bank_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sizeof(struct stm32_exti_chip_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!host_data->chips_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto free_host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) host_data->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!host_data->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pr_err("%pOF: Unable to map registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto free_chips_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) stm32_host_data = host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) free_chips_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) kfree(host_data->chips_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) free_host_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) kfree(host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 bank_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) const struct stm32_exti_bank *stm32_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct stm32_exti_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void __iomem *base = h_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) stm32_bank = h_data->drv_data->exti_banks[bank_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) chip_data = &h_data->chips_data[bank_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) chip_data->host_data = h_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) chip_data->reg_bank = stm32_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) raw_spin_lock_init(&chip_data->rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * This IP has no reset, so after hot reboot we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * clear registers to avoid residue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writel_relaxed(0, base + stm32_bank->imr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) writel_relaxed(0, base + stm32_bank->emr_ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pr_info("%pOF: bank%d\n", node, bank_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct stm32_exti_host_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int nr_irqs, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) host_data = stm32_exti_host_init(drv_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!host_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &irq_exti_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pr_err("%pOFn: Could not register interrupt domain.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) handle_edge_irq, clr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pr_err("%pOF: Could not allocate generic interrupt chip.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) for (i = 0; i < drv_data->bank_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) const struct stm32_exti_bank *stm32_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct stm32_exti_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) stm32_bank = drv_data->exti_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) chip_data = stm32_exti_chip_init(host_data, i, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) gc->reg_base = host_data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) gc->chip_types->chip.irq_ack = stm32_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) gc->suspend = stm32_irq_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) gc->resume = stm32_irq_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) gc->chip_types->regs.mask = stm32_bank->imr_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) gc->private = (void *)chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) nr_irqs = of_irq_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) unsigned int irq = irq_of_parse_and_map(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) irq_set_handler_data(irq, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) irq_set_chained_handler(irq, stm32_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) iounmap(host_data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) kfree(host_data->chips_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) kfree(host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const struct irq_domain_ops stm32_exti_h_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .alloc = stm32_exti_h_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static void stm32_exti_remove_irq(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct irq_domain *domain = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int stm32_exti_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) stm32_exti_h_syscore_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int stm32_exti_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct irq_domain *parent_domain, *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct stm32_exti_host_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const struct stm32_exti_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!host_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* check for optional hwspinlock which may be not available yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = of_hwspin_lock_get_id(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* hwspinlock framework not yet ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!host_data->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(dev, "Failed to request hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else if (ret != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* note: ENOENT is a valid case (means 'no hwspinlock') */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(dev, "Failed to get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* initialize host_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) drv_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!drv_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(dev, "no of match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) host_data->drv_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) sizeof(*host_data->chips_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!host_data->chips_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) host_data->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (IS_ERR(host_data->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(dev, "Unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return PTR_ERR(host_data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) for (i = 0; i < drv_data->bank_nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) stm32_exti_chip_init(host_data, i, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) parent_domain = irq_find_host(of_irq_find_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(dev, "GIC interrupt-parent not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) domain = irq_domain_add_hierarchy(parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) drv_data->bank_nr * IRQS_PER_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) np, &stm32_exti_h_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(dev, "Could not register exti domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) stm32_exti_h_syscore_init(host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* platform driver only for MP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const struct of_device_id stm32_exti_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MODULE_DEVICE_TABLE(of, stm32_exti_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct platform_driver stm32_exti_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .probe = stm32_exti_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .remove = stm32_exti_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "stm32_exti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .of_match_table = stm32_exti_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int __init stm32_exti_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return platform_driver_register(&stm32_exti_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static void __exit stm32_exti_arch_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return platform_driver_unregister(&stm32_exti_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) arch_initcall(stm32_exti_arch_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) module_exit(stm32_exti_arch_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* no platform driver for F4 and H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static int __init stm32f4_exti_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return stm32_exti_init(&stm32f4xx_drv_data, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int __init stm32h7_exti_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return stm32_exti_init(&stm32h7xx_drv_data, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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