^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Socionext External Interrupt Unit (EXIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on irq-tegra.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2010,2013, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NUM_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EIMASK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EISRCSEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EIREQSTA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EIRAWREQSTA 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EIREQCLR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EILVL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EIEDG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EISIR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct exiu_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void exiu_irq_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writel(BIT(d->hwirq), data->base + EIREQCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void exiu_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) writel_relaxed(val, data->base + EIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void exiu_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel_relaxed(val, data->base + EIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void exiu_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* clear interrupts that were latched while disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(val, data->base + EIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irq_chip_enable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = readl_relaxed(data->base + EILVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(val, data->base + EILVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val = readl_relaxed(data->base + EIEDG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel_relaxed(val, data->base + EIEDG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct irq_chip exiu_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "EXIU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .irq_eoi = exiu_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .irq_enable = exiu_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .irq_mask = exiu_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .irq_unmask = exiu_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .irq_set_type = exiu_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .flags = IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) IRQCHIP_SKIP_SET_WAKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) IRQCHIP_EOI_THREADED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int exiu_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct exiu_irq_data *info = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (fwspec->param[0] != GIC_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EINVAL; /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *hwirq = fwspec->param[1] - info->spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct exiu_irq_data *info = dom->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) parent_fwspec = *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (is_of_node(dom->parent->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -EINVAL; /* Not GIC compliant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (fwspec->param[0] != GIC_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL; /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) hwirq = fwspec->param[1] - info->spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) parent_fwspec.param[0] = hwirq + info->spi_base + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) WARN_ON(nr_irqs != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) parent_fwspec.fwnode = dom->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct irq_domain_ops exiu_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .translate = exiu_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .alloc = exiu_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct exiu_irq_data *exiu_init(const struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct exiu_irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &data->spi_base, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data->base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!data->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* clear and mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int __init exiu_dt_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct irq_domain *parent_domain, *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct exiu_irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pr_err("%pOF: no parent, giving up\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_err("%pOF: unable to obtain parent domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (of_address_to_resource(node, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("%pOF: failed to parse memory resource\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) data = exiu_init(of_node_to_fwnode(node), &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &exiu_domain_ops, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_err("%pOF: failed to allocate domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) iounmap(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int exiu_acpi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct exiu_irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(&pdev->dev, "failed to parse memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) data = exiu_init(dev_fwnode(&pdev->dev), res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) domain = acpi_irq_create_hierarchy(0, NUM_IRQS, dev_fwnode(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &exiu_domain_ops, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&pdev->dev, "failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) iounmap(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct acpi_device_id exiu_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { "SCX0008" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DEVICE_TABLE(acpi, exiu_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_driver exiu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "exiu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .acpi_match_table = exiu_acpi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .probe = exiu_acpi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) builtin_platform_driver(exiu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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